Register Space - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2022-04-26
Version
5.1 English

This section details registers available in the MIPI CSI-2 RX Subsystem. The address map is split into following regions:

MIPI CSI-2 RX Controller core

MIPI D-PHY core

Each IP core is given an address space of 4K. Example offset addresses from the system base address when the MIPI D-PHY registers are enabled are shown in Table: Sub-Core Address Offsets .

Table 2-6: Sub-Core Address Offsets

IP Cores

Offset

MIPI CSI-2 RX Controller

0x0_0000

MIPI D-PHY

0X0_1000