Selecting Shared Logic in the Core implements the subsystem with the PLL inside the subsystem to generate all the clocking requirement of the PHY layer.
Select Include Shared Logic in Core if:
• You do not require direct control over the PLL generated clocks
• You want to manage multiple customizations of the subsystem for multi-subsystem designs
• This is the first MIPI CSI-2 RX Subsystem in a multi-subsystem system
These components are included in the subsystem, and their output ports are also provided as subsystem outputs.