Tclk-Post Requirement - 5.1 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2022-04-26
Version
5.1 English

MIPI CSI-2 Rx Subsystem needs TCLK-POST to be a minimum of 18 rxbyteclkhs. MIPI D-PHY v2.0 recommends the minimum value of TCLK-POST as 60ns +52UI. The system designer should consider the maximum of these two TCLK-POST values for the MIPI source.

For example,

1. For a line-rate of 896 Mbps, rxbyteclkhs is 1.116ns. The required TCLK-POST is
18*1.116 = 20.089ns

2. Example s for specific line-rates are as follows:

Table 1-2: Line-rate Specific Example

Linerate

EQ1: TCLK-POST minimum per D-PHY 2.0 specification (60ns +52UI)

EQ2:Required TCLK-POST minimum by MIPI CSI-2 Rx Subsystem

Final TCLK-POST MAX(EQ1, EQ2)

896

118ns

160ns

160ns

1440

96ns

100ns

100ns

2000

86ns

72ns

86ns

TCLK-POST is the setting in the Transmitter (D-PHY or CSI-2) which the system designer has to set based on the receiver requirements.