The Hard Block Planner window allows you to place the hard blocks within a device and provides a visual feedback in the Device window for assigning the location of the REFCLK pins, the GT_QUADs, and the Hard-IP blocks. Once you open the synthesized design, it reads and processes the netlist objects and collects all hard IPs available in a design. This planner allows you to cross-probe the location in the device window view for changing or assigning the site.
Figure 1. Hard Block Planner Window
To view the Hard Block Planner window, open Synthesized/Implemented design. The Hard Block Planner window opens by default after opening Synthesized/Implemented design. Alternately, it can be opened from the Windows menu
Hard Block Planner Window Columns
The Hard Block Planner window has the following columns:- Name: Specifies the instance name of the hard block.
- Library Cell: Provides the library name of the hard block.
- Site: Provides the location of the library cell instance.
- Fixed: Specifies whether the BEL location is fixed or not.
- Clock Region: Specifies the clock region.
- Bank: Specifies the bank.
- REFCLK Source: Provides the clock name of the reference clock.
Hard Block Planner Window Tool Bar Commands
The local tool bar contains the following commands:- Search: Opens the search bar to allow you to quickly locate objects in the hard block planner window.
- Collapse All: Collapses all hierarchical tree objects to display only the top-level objects.
- Expand All: Expands all hierarchical tree objects to display all elements of the hard block planner window.
- Schematic: Creates a schematic from the selected objects.
- Show Hard-IP Connectivity: Selects and displays all GTs and IPs of the design on the device view.
- Show Hard-IP Connectivity for selected IP groups: Selects and displays all GTs and IPs of the design on the device view for the selected IP Group.
- Hide Hard-IP Connectivity: Deselects all GTs and IPs of the design on the device view.