Resource utilization metrics for the SEM Controller are derived from post-synthesis reports and are for budgetary purposes only. Actual resource utilization might vary.
Device |
IP Core Configuration |
LUTs |
FFs |
I/Os |
Block RAMs |
---|---|---|---|---|---|
Zynq 7000
|
Complete solution with no optional features |
509 |
361 |
11 |
3 RAMB18 |
Zynq 7000
|
Complete solution with all optional features |
877 |
673 |
56 |
3 RAMB18, 2 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
912 |
674 |
56 |
3 RAMB18, 3 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
912 |
674 |
56 |
3 RAMB18, 3 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
863 |
681 |
56 |
3 RAMB18, 2 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
834 |
682 |
58 |
3 RAMB18, 3 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
838 |
682 |
56 |
3 RAMB18, 3 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
887 |
683 |
56 |
3 RAMB18, 5 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
994 |
696 |
56 |
3 RAMB18, 10 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
994 |
696 |
56 |
3 RAMB18, 10 RAMB36 |
Zynq 7000
|
Complete solution with all optional features |
1,065 |
696 |
56 |
3 RAMB18, 13 RAMB36 |
Notes: 1. The complete solution is the SEM Controller and the example design, which are intended to be used together. 2. The Error Injection Interface is connected to I/Os; use of logic debug IP (VIO) increases LUTs/FFs but decreases I/Os. |
Device |
IP Core Configuration |
LUTs |
FFs |
I/Os |
Block RAMs |
---|---|---|---|---|---|
Kintex 7
|
Complete solution with no optional features |
511 |
361 |
11 |
3 RAMB18 |
Kintex 7
|
Complete solution with all optional features |
849 |
682 |
56 |
3 RAMB18, 3 RAMB36 |
Kintex 7
|
Complete solution with all optional features |
887 |
683 |
56 |
3 RAMB18, 5 RAMB36 |
Kintex 7
|
Complete solution with all optional features |
991 |
686 |
56 |
3 RAMB18, 9 RAMB36 |
Kintex 7
|
Complete solution with all optional features |
994 |
696 |
56 |
3 RAMB18, 10 RAMB36 |
Kintex 7
|
Complete solution with all optional features |
1,028 |
696 |
56 |
3 RAMB18, 11 RAMB36 |
Kintex 7 XC7K420T |
Complete solution with all optional features |
1,065 |
696 |
56 |
3 RAMB18, 13 RAMB36 |
Kintex 7
|
Complete solution with all optional features |
1,065 |
696 |
56 |
3 RAMB18, 13 RAMB36 |
Kintex 7 Low Voltage, Kintex 7Q, Kintex 7Q Low Voltage, All Devices |
Same as Kintex 7 |
||||
Notes: 1. The complete solution is the SEM Controller and the example design, which are intended to be used together. 2. The Error Injection Interface is connected to I/Os; use of logic debug IP (VIO) increases LUTs/FFs but decreases I/Os. |
Device |
IP Core Configuration |
LUTs |
FFs |
I/Os |
Block RAMs |
---|---|---|---|---|---|
Virtex 7
|
Complete solution with no optional features |
510 |
361 |
11 |
3 RAMB18 |
Virtex 7
|
Complete solution with all optional features |
996 |
696 |
56 |
3 RAMB18, 10 RAMB36 |
Virtex 7
|
Complete solution with all optional features |
1,065 |
696 |
56 |
3 RAMB18, 12 RAMB36 |
Virtex 7
|
Complete solution with all optional features |
1,101 |
697 |
56 |
3 RAMB18, 14 RAMB36 |
Virtex 7
|
Complete solution with all optional features |
1,218 |
691 |
56 |
3 RAMB18, 20 RAMB36 |
Virtex 7
|
Complete solution with all optional features |
1,073 |
698 |
56 |
3 RAMB18, 15 RAMB36 |
Virtex 7
|
Complete solution with all optional features |
1,218 |
691 |
56 |
3 RAMB18, 20 RAMB36 |
Virtex 7
|
Complete solution with all optional features |
1,366 |
692 |
56 |
3 RAMB18, 26 RAMB36 |
Virtex 7Q
|
Same as Virtex 7 |
||||
Notes: 1. The complete solution is the SEM Controller and the example design, which are intended to be used together. 2. The Error Injection Interface is connected to I/Os; use of logic debug IP (VIO) increases LUTs/FFs but decreases I/Os. |
Device |
IP Core Configuration |
LUTs |
FFs |
I/Os |
Block RAMs |
---|---|---|---|---|---|
Virtex 7
|
Complete solution with no optional features |
1,394 |
980 |
19 |
7 RAMB18 |
Virtex 7
|
Complete solution with all optional features |
2,410 |
1,692 |
64 |
7 RAMB18, 18 RAMB36 |
Virtex 7
|
Complete solution with no optional features |
1,853 |
1,289 |
27 |
10 RAMB18 |
Virtex 7
|
Complete solution with all optional features |
3,245 |
2,230 |
72 |
10 RAMB18, 27 RAMB36 |
Virtex 7
|
Complete solution with no optional features |
2,245 |
1,598 |
35 |
13 RAMB18 |
Virtex 7
|
Complete solution with all optional features |
4,032 |
2,768 |
80 |
13 RAMB18, 36 RAMB36 |
Virtex 7
|
Complete solution with no optional features |
2,256 |
1,598 |
35 |
13 RAMB18 |
Virtex 7
|
Complete solution with all optional features |
4,342 |
2,808 |
80 |
13 RAMB18, 48 RAMB36 |
Virtex 7Q,
|
Same as Virtex 7 |
||||
Notes: 1. The complete solution is the SEM Controller and the example design, which are intended to be used together. 2. The Error Injection Interface is connected to I/Os; use of logic debug IP (VIO) increases LUTs/FFs but decreases I/Os. |
Device |
IP Core Configuration |
LUTs |
FFs |
I/Os |
Block RAMs |
---|---|---|---|---|---|
Artix 7
|
Complete solution with no optional features |
512 |
361 |
11 |
3 RAMB18 |
Artix 7 XC7A12T |
Complete solution with all optional features |
877 |
673 |
56 |
3 RAMB18, 2 RAMB36 |
Artix 7 XC7A15T |
Complete solution with all optional features |
800 |
681 |
56 |
3 RAMB18, 2 RAMB36 |
Artix 7 XC7A25T |
Complete solution with all optional features |
877 |
673 |
56 |
3 RAMB18, 2 RAMB36 |
Artix 7 XC7A35T |
Complete solution with all optional features |
802 |
681 |
56 |
3 RAMB18, 2 RAMB36 |
Artix 7 XC7A50T |
Complete solution with all optional features |
800 |
681 |
56 |
3 RAMB18, 2 RAMB36 |
Artix 7
|
Complete solution with all optional features |
837 |
682 |
56 |
3 RAMB18, 3 RAMB36 |
Artix 7 XC7A100T |
Complete solution with all optional features |
837 |
682 |
56 |
3 RAMB18, 3 RAMB36 |
Artix 7 XC7A200T |
Complete solution with all optional features |
919 |
681 |
56 |
3 RAMB18, 7 RAMB36 |
Artix 7 Low Voltage, Artix 7A, Artix 7Q, All Devices |
Same as Artix 7 |
||||
Notes: 1. The complete solution is the SEM Controller and the example design, which are intended to be used together. 2. The Error Injection Interface is connected to I/Os; use of logic debug IP (VIO) increases LUTs/FFs but decreases I/Os. |
Device |
IP Core Configuration |
LUTs |
FFs |
I/Os |
Block RAMs |
---|---|---|---|---|---|
Spartan 7
|
Complete solution with no optional features |
498 |
406 |
11 |
3 RAMB18 |
Spartan 7 XC7S6 |
Complete solution with all optional features |
842 |
673 |
56 |
3 RAMB18, 1 RAMB36 |
Spartan 7 XC7S15 |
Complete solution with all optional features |
842 |
673 |
56 |
3 RAMB18, 1 RAMB36 |
Spartan 7 XC725 |
Complete solution with no optional features |
877 |
673 |
56 |
3 RAMB18, 2 RAMB36 |
Spartan 7 XC7S50 |
Complete solution with all optional features |
877 |
673 |
56 |
3 RAMB18, 2 RAMB36 |
Spartan 7 XC7S75 |
Complete solution with all optional features |
912 |
674 |
56 |
3 RAMB18, 3 RAMB36 |
Spartan 7 XC7S100 |
Complete solution with all optional features |
912 |
674 |
56 |
3 RAMB18, 3 RAMB36 |
Notes: 1. The complete solution is the SEM Controller and the example design, which are intended to be used together. 2. The Error Injection Interface is connected to I/Os; use of logic debug IP (VIO) increases LUTs/FFs but decreases I/Os. |