Product Qualification

Device Reliability Report (UG116)
Document ID
UG116
Release Date
2023-05-17
Revision
10.17 English

The reliability tests used for wafer process qualification are summarized in the following table.

Table 1. Wafer Process Qualification Tests
Reliability Test Conditions Duration Lot Quantity Sample Size per Lot Acceptance Criteria
High-temperature operating life (HTOL) TJ ≥ 125°C, VDD Max 1,000 hours 3 77

200 FIT 1

50 FIT 2

THB 3 or Highly accelerated temperature and humidity stress test (HAST) 3 85°C, 85% RH, VDD 1,000 hours 3 25 0 failures
130°C, 85% RH, VDD 96 hours
110°C, 85% RH, V DD 264 hours
Temperature humidity (TH) 3 or Unbiased highly accelerated temperature and humidity stress test (UHAST) 3 85°C, 85% RH 1,000 hours 3 25 0 failures
130°C, 85% RH 96 hours
110°C, 85% RH 264 hours
Temperature cycling (TC) 3, 4, 5, 6, –65°C to +150°C 500 cycles 3 25 0 failures
–55°C to+125°C 1,000 cycles
–40°C to +125°C 1,000 cycles
Data Retention Bake 7 or High Temperature Storage (HTS) TA = 150°C 1,000 hours 3 25 0 failures
Program Erase 8 TA = 25°C 10,000 cycles 1 32 0 failures
  1. FIT is failure in time. Phase I production is released as the qualification data demonstrates, meeting the required 200 FIT failure rate and other test requirements.
  2. Phase II production is released as the qualification data demonstrates, meeting the required 50 FIT failure rate and other test requirements.
  3. Package preconditioning is performed prior to THB, HAST, temperature cycling, TH, and UHAST tests.
  4. For plastic QFP packages: –65°C to +150°C and 500 cycles or –55°C to +125°C and 1,000 cycles.
  5. For plastic BGA packages: –55°C to +125°C and 1,000 cycles.
  6. For flip chip packages: –55°C to +125°C and 1,000 cycles or –40°C to +125°C and 1,000 cycles.
  7. For CPLD and EPROM products.
  8. This is not a mandatory test and only for CPLD and EPROM products.