SEU and Soft Error Rate Measurements

Device Reliability Report (UG116)

Document ID
UG116
Release Date
2023-05-17
Revision
10.17 English

Table 1, Table 2, and Table 3 show the soft error rates caused by single event upsets (SEUs) affecting memory cells used as configuration RAM, block RAM, and UltraRAM. Neutron cross-sections are determined from LANSCE beam testing according to JESD89A/89-3A. Soft error rates (in FIT/Mb) are determined from real-time (system level) measurements in various locations and altitudes and corrected for New York City, according to JESD89A/89-1A. Also refer to Continuing Experiments of Atmospheric Neutron Effects on Deep Submicron Integrated Circuits (WP286). All data is current as of the date of this report.

An upset in any configuration bit does not create a soft functional error per se. The bit has to be one that is critical to the function in order for a soft functional error to occur. The number of unused bits and non-critical bits reduces the effective soft error rate by what is known as the device vulnerability factor (DVF). The DVF for a typical design is 5% (one in 20 upsets, on average, cause a functional soft error). In the worst case, the DVF is never larger than one in ten, or never more than 10% of the upsets cause a soft functional error. Therefore, the functional soft error rate of a design running in programmable logic is far lower than what is predicted by calculation from the data in Table 1, Table 2, and Table 3. The significant factor contributing to low DVF is that most programmable logic routing resources are unused within any particular implementation.

AMD offers a significant portfolio of SEU analysis and mitigation solutions to help you understand and interpret soft error rates and manage SEU rates in any given design. Consult your AMD sales and field support for assistance in understanding these capabilities, and visit our Single Event Upsets website to obtain the AMD SEU Estimator tool for modeling device-level SEU rates based on operating environment and the data in Table 1, Table 2, and Table 3. The AMD SEU Estimator tool models total SEU rate in terrestrial environments by scaling the real-time data based on operating environment and adding the alpha particle data.

In Table 1, Table 2, and Table 3, Tech Node is technology node, CRAM is configuration RAM, BRAM is block RAM, and URAM is UltraRAM. The data in these tables is not a specification but is for reference only, under the stated conditions for each experiment.

Table 1. Experimental Beam Testing and Real-Time Soft Error Rates for CRAM 1 . All experiments are performed at ambient temperature with typical power supply voltages.
Tech Node Product Family LANSCE Neutron Cross-Section per Bit 2 FIT/Mb (Thermal Neutrons) FIT/Mb (Alpha Particle) 3 FIT/Mb 4 (Real-Time Soft Error Rate Per Event) 5, 7
CRAM Error CRAM Error 6 CRAM Error 6 CRAM Error 6
90 nm Virtex-4 1.55 x 10-14 ±18%         263 ±11%
90 nm Spartan-3 2.40 x 10-14 ±18%         190 –50%

+80%

90 nm Spartan-3E, Spartan-3A 1.31 x 10-14 ±18%         104 –80%

+90%

65 nm Virtex-5 6.70 x 10-15 ±18%         165 –13%

+15%

45 nm Spartan-6 1.00 x 10-14 ±18% 21 –11%

+13%

88 –50%

+100%

177 –10%

+11%

40 nm Virtex-6 1.26 x 10-14 ±18% 0.7 –11%

+13%

7 –45%

+97%

105 –10%

+11%

28 nm Artix 7, Spartan 7, and Zynq 7000 6.99 x 10-15 ±18% 29 –10%

+10%

50 –34%

+56%

74 –8%

+9%

28 nm Kintex 7 and Virtex 7 5.69 x 10-15 ±18% 1.1 –15%

+18%

50 –34%

+56%

40 –17%

+21%

20 nm UltraScale 2.55 x 10-15 ±18% 0.5 –13%

+16%

9 –64%

+374%

32 –10%

+12%

16 nm UltraScale+ 2.67 x 10-16 ±18% 0.35 –16%

+20%

0.1 –20%

+20%

5 –16%

+20%

7 nm Versal 2.6 x 10-17 ±20% 0.1 ±50% 0.1 ±50% 0.7 ±50%
  1. Experiments are performed at ambient temperature with typical power supply voltages.
  2. Data from Los Alamos Neutron Science Center (LANSCE).
  3. Spartan-6, UltraScale+, and Versal device alpha data is based on alpha foil testing and package alpha emissivity of 0.001 counts/cm2/hr. Virtex-6, 7 series, and UltraScale FPGA alpha data estimated using real-time underground cave testing.
  4. One FIT equals 1 failure per 1 billion device hours. Mb = 1e6 memory bits.
  5. Data compiled from Rosetta experiment which includes upsets from neutron, proton, and thermal neutron secondaries. Based on experimental methodology, upsets from alpha particles are not included. Modeling of the total SEU rate in terrestrial environments requires use of alpha particle data in addition to real-time data. AMD advises use of the SEU Estimator tool to model total SEU rates.
  6. 90% confidence interval.
  7. Soft error rates (in FIT/Mb) are determined from real-time (system level) measurements in various locations and altitudes and corrected for New York City, according to JESD89A/89-1A.
Table 2. Experimental Beam Testing and Real-Time Soft Error Rates for BRAM 1
Tech Node Product Family LANSCE Neutron Cross-Section per Bit 2 FIT/Mb (Thermal Neutrons) FIT/Mb (Alpha Particle) 3 FIT/Mb 4 (Real-Time Soft Error Rate Per Event) 5, 7
BRAM Error BRAM Error 6 BRAM Error 6 BRAM Error 6
90 nm Virtex-4 2.74 x 10-14 ±18%         484 ±11%
90 nm Spartan-3 3.48 x 10-14 ±18%         373 –50%

+80%

90 nm Spartan-3E, Spartan-3A 2.73 x 10-14 ±18%         293 –80%

+90%

65 nm Virtex-5 3.96 x 10-14 ±18%         692 –13%

+15%

45 nm Spartan-6 2.20 x 10-14 ±18% 83 –11%

+13%

172 –50%

+100%

370 –10%

+11%

40 nm Virtex-6 1.14 x 10-14 ±18% 1.4 –11%

+13%

120 –45%

+97%

213 –10%

+11%

28 nm Artix 7, Spartan 7, and Zynq 7000 6.32 x 10-15 ±18% 41 –10%

+10%

45 –34%

+56%

72 –8%

+9%

28 nm Kintex 7 and Virtex 7 5.57 x 10-15 ±18% 1.8 –15%

+18%

45 –34%

+56%

42 –23%

+31%

20 nm UltraScale 4.43 x 10-15 ±18% 1.1 –13%

+16%

16 –64%

+374%

58 –15%

+18%

16 nm UltraScale+ 9.82 x 10-16 ±18% 4.7 –12%

+13%

7 –20%

+20%

15 –13%

+15%

7 nm Versal 1.2 x 10-15 ±20% 2.0 ±50% 2.0 ±50% 15 ±50%
  1. Experiments are performed at ambient temperature with typical power supply voltages.
  2. Data from Los Alamos Neutron Science Center (LANSCE).
  3. Spartan-6, UltraScale+, and Versal device alpha data is based on alpha foil testing and package alpha emissivity of 0.001 counts/cm2/hr. Virtex-6, 7 series, and UltraScale FPGA alpha data is estimated using real-time underground cave testing.
  4. One FIT equals 1 failure per 1 billion device hours. Mb = 1e6 memory bits.
  5. Data compiled from Rosetta experiment which includes upsets from neutron, proton, and thermal neutron secondaries. Based on experimental methodology, upsets from alpha particles are not included. Modeling of the total SEU rate in terrestrial environments requires use of alpha particle data in addition to real-time data. AMD advises use of the SEU Estimator tool to model total SEU rates.
  6. 90% confidence interval.
  7. Soft error rates (in FIT/Mb) are determined from real-time (system level) measurements in various locations and altitudes and corrected for New York City, according to JESD89A/89-1A.
Table 3. Experimental Beam Testing and Real-Time Soft Error Rates for URAM 1
Tech Node Product Family LANSCE Neutrons Cross-Section per Bit 2 FIT/Mb 3, 5 (Thermal Neutrons) FIT/Mb (Alpha Particle) 4, 5 FIT/Mb (Real-Time Soft Error Rate Per Event) 5, 7
URAM Error URAM Error 6 URAM Error 6 URAM Error
16 nm UltraScale+ 8.06 x 10–16 ±20% 4.1 ±50% 6.2 ±20% 10.2 ±20%
7 nm Versal 3.0 x 10–16 ±20% 0.5 ±50% 0.5 ±50% 2.0 ±50%
  1. Experiments are performed at ambient temperature with typical power supply voltages.
  2. Data from Los Alamos Neutron Science Center (LANSCE).
  3. Estimate based on BRAM/URAM neutron ratio.
  4. UltraScale+ and Versal device alpha data is based on alpha foil testing and package alpha emissivity of 0.001 counts/cm2/hr.
  5. One FIT equals 1 failure per 1 billion device hours. Mb = 1e6 memory bits.
  6. 90% confidence interval.
  7. Soft error rates (in FIT/Mb) are determined from real-time (system level) measurements in various locations and altitudes and corrected for New York City, according to JESD89A/89-1A.