Crest factor reduction (CFR) is used to limit the dynamic range of the signals being transmitted in wireless communications and other applications. Multi-user and multi-carrier signals often have a high peak-to-average ratio (PAR). This places high demands on the data converters and especially limits the efficiency of operation of the power amplifiers (PAs) used in cellular base stations. Reducing the PAR is therefore beneficial in increasing PA efficiency by allowing higher average power to be transmitted before saturation occurs.
In a modern transmit chain, CFR is often incorporated with digital pre-distortion (DPD), which acts to linearize the PA, allowing operation at maximum efficiency with spectral compliance. CFR complements DPD because it levels the signal peaks, making accurate correction estimation easier.
The Xilinx PC-CFR core is an efficient, flexible, and easy-to-use implementation that supports Virtex UltraScale, Kintex UltraScale, Virtex-7, Kintex-7, Artix-7, and Zynq UltraScale+ devices (Zynq SoC, MPSoC, and RFSoC). On a Zynq UltraScale+ RFSoC DFE device, the PC-CFR allows for selection of the PL-only option or use of the DFE-CFR Primitive along with PL resources. It is configurable both in function, supporting all major cellular wireless air interfaces, and in use, supporting many clocking and resource requirements. It can also handle dynamic power and frequency variations in the incoming data by computing the cancellation pulse coefficients dynamically.