When you create a block design, the BD file (.bd extension) is saved to the project source file. IP integrator BD sources cannot be directly synthesized in the Vivado tools. There are two ways to instantiate a BD file:
- BD top
The BD file is instantiated in a top-level RTL file. The top-level RTL is a wrapper that can be automatically generated and contains only a single instance of the BD. This approach is recommended but not required for Versal ACAP designs.
This approach ensures that the hardware handoff to the system software occurs seamlessly and uses the recommended Versal ACAP design structure. The software is aware of all addressable components in the design and ensures that the device tree and drivers are created properly.
- RTL top
The BD file as well as custom logic and IP are instantiated in atop-level RTL file. In some cases, one or more BD files can also be instantiated in sub-levels of the hierarchy.
This approach allows the most flexibility for traditional designs migrating to Versal ACAP. Successful hardware handoff in the RTL top approach is only supported if the complete addressing scope is contained to a single BD instantiated in the hierarchy below the top-level RTL file. In any other scenario, the designer is responsible for creating the device tree and loading the necessary software drivers.
The following sections focus on how to incorporate design sources into a block diagram.