When multiple Versal devices on a PCB have to be fed with the same clock, and the design on the board needs to run synchronously, it is common practice to pass the clock source through a multi-clock buffer on the board, and adjust the length of the clock routes/lanes between the clock buffer device, and the different Versal devices on the PCB.
Using a DESKEW unit in an MMCM or PLL can achieve the same result without external multi-zero delay clock buffer and careful timing routed PCB tracks. The following figure shows a two-Versal device example and how it can be achieved.
Figure 1. Deskew of External Versal
Device Clocks - System Synchronous
Design
The setup demonstrated here is between two Versal devices.
- The System Clock in both devices can be any master clock necessary to generate clocks for logic, hard-IP and/or soft-IP.
- In both devices, CLKOUT4 (Clock Two) is used as clock that needs to be phase aligned between the two devices.
- The PCB traces from Clock Source to adaptive SoC #1 (A) is shorter than the clock traces between the Clock Source and adaptive SoC #2 (B).
- The key requirement is that CLKIN and CLKIN_DESKEW in each device must have a common reference point, which in this case is the clock source oscillator.
- How does it work?
- The differential clock input buffers (IBUFDS) are handled as zero delay buffers.
- The programmable delay is handled as if it has no initial delay.
- In both devices, the setup around the MMCM is identical. CLKOUT4 is used as feedback clock for the DESKEW unit while the clock input of the unit is connected to a clock input. This setup will phase align the output of the clock buffer connected to CLKOUT4 to the CLKIN_DESKEW of the MMCM.
- The DESKEW unit setup in adaptive SoC #2 is straightforward. Feed the input clock and feedback clock to the DESKEW unit and let it phase align clock two to the input clock.
- The DESKEW unit setup in adaptive SoC #1 uses the programmable delay to compensate for the longer clock route to adaptive SoC #2. The programmable delay is engaged in the clock input path and is set to a value of: PRGDLY = Trace B –Trace A.
- Using the delay line in the DESKEW unit of the MMCM in adaptive SoC #1 allows the clock traces between the clock source and both devices are of equal length. As such, this ensures that both clocks are phase-aligned.