The following table shows the AXI HBM controller signals.
Port Name | I/O | Description |
---|---|---|
AXI_xx_ACLK | I | Clock for the AXI Interface |
AXI_xx_ARESET_N | I | Active-Low AXI Reset. This reset port should only be used prior
to the start of data traffic. Using it after traffic has begun will cause the AXI
interface and the memory controller to become out-of-sync. When the switch is enabled, the IP will internally connect all of the AXI_xx_ARESET_N pins together because the memory behaves as a single unit. |
AXI_xx_ARADDR | I | [32:0] Read Address for 4H Stack, [33:0] Read Address for 8H Stack 2 |
AXI_xx_ARBURST | I | [1:0] Address Read Burst. The fixed address burst type (2'b00) is not supported |
AXI_xx_ARID | I | [5:0] Read Address ID Tag |
AXI_xx_ARLEN | I | [3:0] Read Burst Length |
AXI_xx_ARSIZE | I |
[2:0] Read Burst Size Only 256-bit size supported (3'b101) |
AXI_xx_ARVALID | I | Read Address Valid |
AXI_xx_ARREADY | O | Read address Ready |
AXI_xx_AWADDR | I | [32:0] Write Address for 4H Stack, [33:0] Write Address for 8H Stack 2 |
AXI_xx_AWBURST | I | [1:0] Write Burst Type. The fixed address burst type (2'b00) is not supported. |
AXI_xx_AWID | I | [5:0] Write Address ID |
AXI_xx_AWLEN | I | [3:0] Write Burst Length |
AXI_xx_AWSIZE | I |
[2:0] Write Burst Only 256-bit size supported (3'b101) |
AXI_xx_AWVALID | I | Write Address Valid |
AXI_xx_RREADY | I | Read Ready |
AXI_xx_BREADY | I | Response Ready |
AXI_xx_WDATA | I | [255:0] Write Data |
AXI_xx_WLAST | I | Write Last |
AXI_xx_WSTRB | I | [31:0] Write Strobe |
AXI_xx_WDATA_PARITY | I | [31:0] Write Data Can be used for user parity or data width expansion. User parity is calculated on a per byte basis and the calculation is Odd. For Odd parity a 1 is asserted per byte if the sum of the bits in that byte is Odd. |
AXI_xx_WVALID | I | Write Valid |
AXI_xx_AWREADY | O | Write Address Ready |
AXI_xx_RDATA_PARITY | O | [31:0] Read Data Parity Can be used for user parity or data width expansion. User parity is calculated on a per byte basis and the calculation is Odd. For Odd parity a 1 is asserted per byte if the sum of the bits in that byte is Odd. |
AXI_xx_RDATA | O | [255:0] Read Data |
AXI_xx_RID | O | [5:0] Read ID Tag |
AXI_xx_RLAST | O | Read Last |
AXI_xx_RRESP | O | [1:0] Read Response |
AXI_xx_RVALID | O | Read Valid |
AXI_xx_WREADY | O | Write Ready |
AXI_xx_BID | O | [5:0] Response ID Tag |
AXI_xx_BRESP | O | [1:0] Write Response |
AXI_xx_BVALID | O | Write Response Valid |
APB_y_PCLK | I | APB Port Clock |
APB_y_PENABLE | I | APB Enable |
APB_y_PRESET_N | I | APB active-Low Reset. When this bit is asserted, it resets the entire memory interface including the controller, PHY, and memory stacks. Runs in the APB_PCLK domain and can be asserted/deasserted asynchronously with a minimum pulse width of one APB clock cycle. |
APB_y_PSEL | I | APB Select |
APB_y_PWRITE | I | APB Bus Direction |
APB_y_PRDATA | O | [31:0] APB Read Data |
APB_y_PREADY | O | APB Ready |
APB_y_PSLVERR | O | APB Transfer Error |
DRAM_y_STAT_CATTRIP | O | HBM Catastrophic Temperature Flag. This bit is asserted when a DRAM's temperature has exceeded 120C. When this bit is asserted, ensure to immediately disable the memory access. |
DRAM_y_STAT_TEMP | O | [6:0] Temperature in Celsius. This is the worst-case scenario for the two memory stacks. When the temperature of the two memory stacks is over 5°C, the highest temperature of the two is driven out on both the DRAM_y_STAT_TEMP ports. When the temperature of the two memory stacks is below 5°C, the lowest temperature of the two stacks is driven out on both the DRAM_y_STAT_TEMP ports. The update frequency is configurable. When there are two ports in the IP for a two Stack enabled design, the data on both ports is identical because it is driven by a single source. 3 |
apb_complete_0 | O | Indicates initial configuration sequence for Stack-0 is complete |
apb_complete_1 | O | Indicates initial configuration sequence for Stack-1 is complete |
|
The following table shows the AXI port assignments in the general interconnect. This includes the start address associated with each HBM channel, memory controller, and pseudo channel to which it is aligned. In non-global address mode, an AXI port can only access its associated pseudo channel. Each AXI port has a fixed address map of 2 Gb (4H Stack) or 4 Gb (8H Stack). Therefore in non-global address mode each AXI port must be mapped to the address space with its start address mentioned in the first column and ending before the start address of the next pseudo channel. In global address mode each port can access all pseudo channels but with varying performance and latency.
Start Address (16 GB) | Start Address (8 GB) | HBM Stack | AXI Port | HBM Channel/PC | HBM Controller |
---|---|---|---|---|---|
0x0_0000_0000 | 0x0_0000_0000 | Left | 0 | A/PC0 | MC0 |
0x0_2000_0000 | 0x0_1000_0000 | Left | 1 | A/PC1 | MC0 |
0x0_4000_0000 | 0x0_2000_0000 | Left | 2 | E/PC0 | MC1 |
0x0_6000_0000 | 0x0_3000_0000 | Left | 3 | E/PC1 | MC1 |
0x0_8000_0000 | 0x0_4000_0000 | Left | 4 | B/PC0 | MC2 |
0x0_A000_0000 | 0x0_5000_0000 | Left | 5 | B/PC1 | MC2 |
0x0_C000_0000 | 0x0_6000_0000 | Left | 6 | F/PC0 | MC3 |
0x0_E000_0000 | 0x0_7000_0000 | Left | 7 | F/PC1 | MC3 |
0x1_0000_0000 | 0x0_8000_0000 | Left | 8 | C/PC0 | MC4 |
0x1_2000_0000 | 0x0_9000_0000 | Left | 9 | C/PC1 | MC4 |
0x1_4000_0000 | 0x0_A000_0000 | Left | 10 | G/PC0 | MC5 |
0x1_6000_0000 | 0x0_B000_0000 | Left | 11 | G/PC1 | MC5 |
0x1_8000_0000 | 0x0_C000_0000 | Left | 12 | D/PC0 | MC6 |
0x1_A000_0000 | 0x0_D000_0000 | Left | 13 | D/PC1 | MC6 |
0x1_C000_0000 | 0x0_E000_0000 | Left | 14 | H/PC0 | MC7 |
0x1_E000_0000 | 0x0_F000_0000 | Left | 15 | H/PC1 | MC7 |
0x2_0000_0000 | 0x1_0000_0000 | Right | 16 | A/PC0 | MC8 |
0x2_2000_0000 | 0x1_1000_0000 | Right | 17 | A/PC1 | MC8 |
0x2_4000_0000 | 0x1_2000_0000 | Right | 18 | E/PC0 | MC9 |
0x2_6000_0000 | 0x1_3000_0000 | Right | 19 | E/PC1 | MC9 |
0x2_8000_0000 | 0x1_4000_0000 | Right | 20 | B/PC0 | MC10 |
0x2_A000_0000 | 0x1_5000_0000 | Right | 21 | B/PC1 | MC10 |
0x2_C000_0000 | 0x1_6000_0000 | Right | 22 | F/PC0 | MC11 |
0x2_E000_0000 | 0x1_7000_0000 | Right | 23 | F/PC1 | MC11 |
0x3_0000_0000 | 0x1_8000_0000 | Right | 24 | C/PC0 | MC12 |
0x3_2000_0000 | 0x1_9000_0000 | Right | 25 | C/PC1 | MC12 |
0x3_4000_0000 | 0x1_A000_0000 | Right | 26 | G/PC0 | MC13 |
0x3_6000_0000 | 0x1_B000_0000 | Right | 27 | G/PC1 | MC13 |
0x3_8000_0000 | 0x1_C000_0000 | Right | 28 | D/PC0 | MC14 |
0x3_A000_0000 | 0x1_D000_0000 | Right | 29 | D/PC1 | MC14 |
0x3_C000_0000 | 0x1_E000_0000 | Right | 30 | H/PC0 | MC15 |
0x3_E000_0000 | 0x1_F000_0000 | Right | 31 | H/PC1 | MC15 |