Core Parameters - 2.1 English

GT Type

Select the GT type. Available options are:

• GTHE4 (Default)
• GTYE4

Data Flow

Select the data flow direction. Available options are:

• Duplex (Default)
• RX-Only
• TX-Only

Unlike Duplex configuration, the RX-Only selection generates the core without GT TX ports and TX-Only selection generates the core with out GT RX ports.

Note: Xilinx UHD-SDI TX subsystem provides an option to generate TX-only example design with PICXO which enables Xilinx UHD-SDI GT core to use with TX-Only data flow option. However, UHD-SDI GT IP core does not provide this option in the core configuration tab.

Line Rate

Select the appropriate line rate. Available options are:

• 12G-SDI
• 6G-SDI
• 3G-SDI

UHD-SDI GT Link(s)

Select the number of link(s). Available options are:

• 1 (Default)
• 2
• 3
• 4

DRP Clock Freq

Provide the DRP clock frequency in MHz. 100 MHz is the default.

Enable PIXCO Ports

Select this option to use the pixco_fraco IP core in your system.

GT COMMON Shared Logic

This option places GT COMMON within the IP Core:

• Include GT COMMON in core (Default)

QPLL0 Ref Clock Selection

Select the reference clock input source for QPLL0. Available options are:

• GTREFCLK0 (Default)
• GTREFCLK1
• GTNORTHREFCLK0
• GTNORTHREFCLK1
• GTSOUTHREFCLK0
• GTSOUTHREFCLK1

QPLL1 Ref Clock Selection

Select the reference clock input source for QPLL1. Available options are:

• GTREFCLK0 (Default)
• GTREFCLK1
• GTNORTHREFCLK0
• GTNORTHREFCLK1
• GTSOUTHREFCLK0
• GTSOUTHREFCLK1

CPLL Ref Clock Selection (Integer)

Select the Integer reference clock input source for CPLL. Available options are:

• GTREFCLK0 (Default)
• GTREFCLK1
• GTNORTHREFCLK0
• GTNORTHREFCLK1
• GTSOUTHREFCLK0
• GTSOUTHREFCLK1

CPLL Ref Clock Selection (Fractional)

Select the Fractional reference clock input source for CPLL. Available options are:

• GTREFCLK0 (Default)
• GTREFCLK1
• GTNORTHREFCLK0
• GTNORTHREFCLK1
• GTSOUTHREFCLK0
• GTSOUTHREFCLK1

The following parameters configure clocking for SDI Link 0:

Link 0 TX Data Width (bits)

Select the Link 0 TX data path width used to configure the transceiver TX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI TX subsystem.

• 40 (default)
• 20

Link 0 RX Data Width (bits)

Select the Link 0 RX data path width used to configure the transceiver RX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI RX subsystem.

• 40 (default)
• 20

Link 0 TX PLL1 Type (integer)

Select the QPLL for TX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 0 RX PLL1 Type (integer)

Select the QPLL for RX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1

Link 0 TX PLL2 Type (fractional)

Select the QPLL for TX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 0 RX PLL2 Type (fractional)

Select the QPLL for RX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1

The following parameters configure clocking for SDI Link 1:

Link 1 TX Data Width (bits)

Select the Link 1 TX data path width used to configure the transceiver TX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI TX subsystem.

• 40 (default)
• 20

Link 1 RX Data Width (bits)

Select the Link 1 RX data path width used to configure the transceiver RX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI RX subsystem.

• 40 (default)
• 20

Link 1 TX PLL1 Type (integer)

Select the QPLL for TX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 1 RX PLL1 Type (integer)

Select the QPLL for RX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1

Link 1 TX PLL2 Type (fractional)

Select the QPLL for TX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 1 RX PLL2 Type (fractional)

Select the QPLL for RX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1

The following parameters configure clocking for SDI Link 2:

Link 2 TX Data Width (bits)

Select the Link 2 TX data path width used to configure the transceiver TX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI TX subsystem.

• 40 (default)
• 20

Link 2 RX Data Width (bits)

Select the Link 2 RX data path width used to configure the transceiver RX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI RX subsystem.

• 40 (default)
• 20

Link 2 TX PLL1 Type (integer)

Select the QPLL for TX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 2 RX PLL1 Type (integer)

Select the QPLL for RX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1

Link 2 TX PLL2 Type (fractional)

Select the QPLL for TX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 2 RX PLL2 Type (fractional)

Select the QPLL for RX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1

The following parameters configure clocking for SDI Link 3:

Link 3 TX Data Width (bits)

Select the Link 3 TX data path width used to configure the transceiver TX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI TX subsystem.

• 40 (default)
• 20

Link 3 RX Data Width (bits)

Select the Link 3 RX data path width used to configure the transceiver RX data path. Select 20 when 3G-SDI or HD-SDI is selected in the SMPTE UHD-SDI RX subsystem.

• 40 (default)
• 20

Link 3 TX PLL1 Type (integer)

Select the QPLL for TX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 3 RX PLL1 Type (integer)

Select the QPLL for RX UHD-SDI integer line rate data path. Available options are:

• QPLL0
• QPLL1

Link 3 TX PLL2 Type (fractional)

Select the QPLL for TX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1
• CPLL

Link 3 RX PLL2 Type (fractional)

Select the QPLL for RX UHD-SDI fractional line rate data path. Available options are:

• QPLL0
• QPLL1