Product Specification - 2.1 English

The Xilinx® UHD-SDI GT core is the supported method of configuring and using transceivers with Xilinx UHD-SDI subsystem IP cores. The core simplifies serial transceiver (GT) use by providing a standardized interface of serial transceiver functions. The functional block diagram of the core is shown in the following figure:

The UHD-SDI GT controller has the following blocks:

Rate Detect Unit

This module is implemented to distinguishes between 1000/1000 and 1000/1001 bit rates of the incoming SDI signal by timing the RXUSRCLK relative to a fixed frequency clock. This module implements two counters. One driven by the reference clock and other driven by the recovered clock. The two counters help in the automatic recognition of the two SDI bit rates. This module looks for the clock frequency change and generates a "rate" signal output whenever there is asynchronous clock switching due to rate change or any other reason. It indicates whenever a drift is seen in the recovered clock beyond a threshold value. This module validates the number of changes before generating the rate_output or clock drift status signals.

Drp_Control

The control module programs the transceiver using the DRP interface. For example, the serial clock divider value of each RX and TX unit can be changed dynamically through the DRP by using the RXOUT_DIV and TXOUT_DIV attributes.

TX_Control

This module modifies attributes in the GTH and GTY transceivers in response to the changes in the TX SDI mode and bit rate. This module is specifically designed to support SDI interfaces implemented in GTH and GTY transceivers. It changes the TXPLLCLKSEL, TXOUT_DIV, TXDATA_WIDTH, and TXINT_DATAWIDTH attributes when the SDI mode and TXPLL input changes.

RX_Control

This module modifies attributes in the GTH and GTY transceivers in response to the changes in the RX SDI mode and bit rate. This module is specifically designed to support SDI interfaces implemented in the GTH and GTY transceivers. It changes the RXPLLCLKSEL, RXCDR_CFG, RXOUT_DIV, RX_DATA_WIDTH, RX_INT_DATA_WIDTH attributes when the SDI mode and RXPLL input changes.

NIDRU

This block is used in applications where lower line rates (those below the rates supported by the respective GTs) are needed. In SDI, the NI-DRU is enabled when the SD-SDI mode is selected. It over samples the data input vector by eleven times in the SD-SDI mode.

The UHD-SDI MULTI-GT wrapper includes the following blocks depending on the core configuration:

Serial Transreceiver GTHE Wrapper

This block instantiates the serial transceivers of a single GTHE quad.

Serial Transreceiver GTYE Wrapper

This block instantiates the serial transceivers of a single GTYE quad.

Serial Transreceiver GTYE Common

This block controls the common primitive of the GTYE serial transceiver. It has the external PLL management and DRP access.

Serial Transreceiver GTHE Common

This block controls the common primitive of the GTHE serial transceiver. It has the external PLL management and DRP access.