Core Specifics |
Supported Device Family
1
|
Kintex®
UltraScale+™
,
Virtex®
UltraScale+™
(GTHE4 & GTYE4),
Zynq®
UltraScale+™ MPSoC (GTHE4 & GTYE4),
Zynq®
UltraScale+™ RFSoC
Artix®
UltraScale+™
|
Supported User Interfaces |
Not Applicable |
Resources |
Performance and Resource Use web page
|
Provided with
Core
|
Design Files |
RTL |
Example Design |
Verilog |
Test Bench |
N/A |
Constraints File |
Xilinx®
Design Constraints
(XDC) |
Simulation Model |
N/A |
Supported S/W Driver |
Not Provided |
Tested Design
Flows
2
|
Design Entry |
Vivado® Design Suite
|
Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Record: 70291
|
All Vivado IP Change
Logs |
Master Vivado IP Change
Logs:72775
|
Xilinx
Support web page
|
- For a complete list of supported devices, see the
Vivado®
IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
- All devices having GTHE4 & GTYE4 transceivers support the UHD-SDI GT
IP.
|