Hardware Testing - 5.0 English

AXI Chip2Chip LogiCORE IP Product Guide (PG067)

Document ID

PG067

Release Date

2022-05-11

Version

5.0 English

This Figure shows the hardware testing setup for the AXI Chip2Chip core.

Figure A-1: AXI Chip2Chip Hardware Testing Setup
X-Ref Target - Figure A-1

The AXI Chip2Chip core with a SelectIO™ FPGA interface has been hardware validated on a KC705 board using a Kintex®–7 FPGA with –1 speed grade (325T). The setup uses two additional FMC loopback cards. Table: Hardware Testing Configuration with a SelectIO FPGA interface provides configuration details for the AXI Chip2Chip core and the frequency achieved by utilizing this setup with the SelectIO ™ interface.

Table A-1: Hardware Testing Configuration with a SelectIO FPGA interface
Features			I/Os Utilized	PHY Clock (MHz)
AXI Data Width	Chip2Chip PHY Type	Chip2Chip PHY Width	Single Ended [HR I/O Banks]	LVCMOS_25 I/O [Unterminated]
32-bit	SelectIO ™ SDR	Compact 4:1	38	200
	SelectIO ™ DDR	Compact 1:1	58	100
	SelectIO ™ DDR	Compact 2:1	32	150
	SelectIO ™ DDR	Compact 4:1	20	150
64-bit	SelectIO ™ DDR	Compact 2:1	46	100
64-bit	SelectIO ™ DDR	Compact 4:1	28	150
Notes: 1. The AXI (system) clock frequency was set to 100 MHz, and the Common Clock mode of operation was selected for configurations having the same PHY clock and AXI clock frequencies (100 MHz).

In addition, XAPP1160 provides a setup demonstrating real-time video traffic across Kintex ® -7 FPGA boards (KC705) and Zynq ® -7000 devices [Ref 1] . This setup uses the AXI Chip2Chip core for connectivity across the FPGA using LPC/HPC connector cables.

The AXI Chip2Chip Aurora Reference Design for Real-Time Video Applications (XAPP1216) demonstrates real-time video traffic between two Kintex ® –7 FPGA KC705 evaluation boards or one KC705 board and one Zynq®-7000 ZC706 evaluation board [Ref 10] . The AXI Chip2Chip core provides connectivity between the two boards using SMA data connector cables.