Common Internal Bus Interfaces - 2022.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2022-10-19
Version
2022.2 English

Some common examples of bus interfaces are buses that conform to the AXI specification such as AXI4, AXI4-Lite, andAXI4-Stream. The AXIMM interface includes all three subsets (AXI4, AXI3, andAXI4-Lite). Other interfaces include block RAM.

I/O Bus Interfaces

Some bus interfaces that group a set of signals going to I/O ports are called I/O interfaces. Examples include: UART, I2C, SPI, Ethernet, PCI™ , and DDR.

Special Signals

Special signals include:

  • Clock
  • Reset
  • Interrupt
  • Clock Enable
  • Data for traditional arithmetic IP which do not have any AXI interface, for example adders, subtractors, and multipliers

These special signals are described in the following sections.

Clock

The clock interface can have the following parameters associated with them. These parameters are used in the design generation process and are necessary when the IP is used with other IP in the design.

  • ASSOCIATED_BUSIF: The list contains the names of all bus interfaces that run at this clock frequency. This parameter takes a colon-separated list (:) of strings as its value.

    If there are no interface signals at the boundary that run at this clock rate, leave this field blank.

    Figure 1. ASSOCIATED_BUSIF

    The previous figure shows the ASSOCIATED_BUSIF parameter of the selected clock interface port and lists the master interfaces (M00_AXI and M01_AXI) and slave interfaces (S00_AXI and S01_AXI) separated by colons.

    If one of the interfaces, such as M00_AXI, does not run at this clock frequency, leave the interface out of the ASSOCIATED_BUSIF parameter for the clock.

  • ASSOCIATED_RESET: The list contains names of reset ports (not names of reset container interfaces) as its value. This parameter takes a colon-separated (:) list of strings as its value. If there are no resets in the design, leave this field blank.
  • ASSOCIATED_CLKEN: The list contains names of clock enable ports (not names of container interfaces) as its value. This parameter takes a colon-separated (:) list of strings as its value. If there are no clock enable signals in the design, leave this field blank.
  • FREQ_HZ: This parameter captures the frequency in hertz at which the clock is running in positive integer format. This parameter needs to be specified for all output clocks only.
  • PHASE: This parameter captures the phase at which the clock is running. The default value is 0. Valid values are 0 to 360. If you cannot specify the PHASE in a fixed manner, then you must update it in bd.tcl, similar to updating FREQ_HZ.
  • CLK_DOMAIN: This parameter is a string ID. By default, IP integrator assumes that all output clocks are independent and assigns a unique ID to all clock outputs across the block design. This is automatically assigned by IP integrator, or managed by IP if there are multiple output clocks of the same domain.

To see the properties on the clock net, select the source clock port or pin and analyze the properties on the object. The following figure shows the Clocking Wizard and the clock properties on the selected pin.

Figure 2. Clock Properties

You can also double-click a port or pin to see the customization dialog box for the selected object.

Reset

This container bus interface includes the POLARITY parameter. Valid values for this parameter are ACTIVE_HIGH or ACTIVE_LOW. The default is ACTIVE_LOW.

To see the properties on the reset net, select the reset port or pin and analyze the properties on the object, as shown in the following figure.

Figure 3. Reset Signal

The following figure shows the Properties window.

Figure 4. Reset Properties Window

Interrupt

This bus interface includes the parameter SENSITIVITY: Valid values for this parameter are LEVEL_HIGH, LEVEL_LOW, EDGE_RISING, and EDGE_FALLING. The default is LEVEL_HIGH.

To see the properties on the interrupt pin, highlight the pin and look at the properties window, as shown in the following figure.

Figure 5. Interrupt Properties: Block Diagram and Properties Window

Clock Enable

There are two parameters associated with Clock Enable: FREQ_HZ and PHASE.