I/O Standard and Placement - 4.1 English

GMII to RGMII Product Guide (PG160)

Document ID
PG160
Release Date
2022-06-15
Version
4.1 English

According to the RGMII v2.0 specification, the I/O pins must use 1.5V HSTL interface voltages. Like the majority of PHYs, those selected for Xilinx development boards are multi-standard and operate at either 1.8V or 2.5V.

A Tcl script that checks the I/O standard of RGMII is included with the IP and can be sourced post-implementation. The Tcl script is located at <project_dir>/<project_name>/<project_name>.srcs/sources1/ip/<component_name>/drc_check/io.

Table: I/O Standards Supported provides information on the I/O standards supported for different Zynq-7000 SoC devices that correspond to the Xilinx 7 series device programmable logic equivalent.

Table 4-2:      I/O Standards Supported

Xilinx 7 Series Device Programmable Logic Equivalent

RGMII Signals Voltage Level Supported

Miscellaneous PHY Signals (MDIO, MDC, RESET) Voltage Level Supported

 

3.3V

2.5V

1.8V

3.3V

2.5V

1.8V

Artix®-7

No(1)

Yes(2)

Yes(3)

Yes(2)

Yes(2)

Yes(3)

Kintex®-7

No(1)

Yes(2)

Yes(3)

Yes(2)

Yes(2)

Yes(3)

Notes:

1.High Range (HR) I/O duty cycle distortion exceeds RGMII specification.

2.Requires the use of HR I/O.

3.Limited 1.8V RGMII-only PHY devices are available. If one of these devices is not used, the external voltage level shifting logic is required.