User Parameters - 1.0 English

MicroBlaze Triple Modular Redundancy (TMR) Subsystem (PG268)

Document ID
PG268
Release Date
2022-04-28
Version
1.0 English

To allow the user to obtain a TMR subsystem that is uniquely tailored a specific use case, certain features can be parameterized in the TMR cores. This allows you to configure a design that only uses the resources required by the system. The features that can be parameterized in TMR cores are shown in Table: TMR Manager Design Parameters to Table: TMR SEM Design Parameters .

Table 4-1: TMR Manager Design Parameters

Feature / Description

Parameter Name

Allowable Values

Default
Value

VHDL
Type

LMB Parameters

TMR Manager base address

C_BASEADDR

Valid address range

0xFFFFFFFF
FFFFFFFF

std_logic_vector

TMR Manager high address

C_HIGHADDR

Valid address range

0x00000000
00000000

std_logic_vector

LMB decode mask

C_MASK

Valid decode mask for LMB

0x00000000
00800000

std_logic_vector

LMB address width

C_LMB_AWIDTH

32 - 64

32

integer

LMB data width

C_LMB_DWIDTH

32

32

integer

TMR Parameters

Magic byte 1

C_MAGIC1

0x00 - 0xFF

0x00

std_logic_vector

Magic byte 2

C_MAGIC2

0x00 - 0xFF

0x00

std_logic_vector

Number of Comparators

C_NO_OF_COMPARATORS

1 - 64

1

integer

Uncorrectable error fatal

C_UE_IS_FATAL

0 = false, 1 = true

0

integer

Uncorrectable error width

C_UE_WIDTH

> 0

3

integer

Illegal miscompare fatal

C_STRICT_MISCOMPARE

0 = false, 1 = true

0

integer

Use Debug Disable input

C_USE_DEBUG_DISABLE

0 = false, 1 = true

0

integer

Use TMR Disable input

C_USE_TMR_DISABLE

0 = false, 1 = true

0

integer

Temporal Lockstep Parameters

This Processor Temporal Depth

C_TEMPORAL_DEPTH_THIS

0 = off, 1 - 31

0

integer

Other Processor Temporal Depth

C_TEMPORAL_DEPTH_OTHER

0 = off, 1 - 31

0

integer

Software Watchdog Parameters

Watchdog enabled

C_WATCHDOG

0 = None
1 = Internal
2 = External

0

integer

Watchdog counter width

C_WATCHDOG_WIDTH

8 - 32

30

integer

SEM Interface Parameters

Enable SEM IP interface

C_SEM_INTERFACE

0 = false, 1 = true

0

integer

SEM interface asynchronous

C_SEM_ASYNC

0 = false, 1 = true

0

integer

Use SEM heartbeat watchdog

C_SEM_HEARTBEAT_
WATCHDOG

0 = false, 1 = true

0

integer

SEM heartbeat watchdog counter width

C_SEM_HEARTBEAT_
WATCHDOG_WIDTH

1 - 32

10

integer

SEM interface type

C_SEM_INTERFACE_TYPE

0 = Unknown
1 = 7 Series
2 = UltraScale
3 = UltraScale+

0

integer

Break delay counter width

C_BRK_DELAY_WIDTH

0 - 32

0

integer

Break delay counter reset value

C_BRK_DELAY_RST_VALUE

Any

0x00000000

std_logic_vector

Test Parameters

Comparator mask enabled

C_COMPARATORS_MASK

0 = false, 1 = true

0

integer

Comparator enable mask reset value

C_MASK_RST_VALUE

Any

0xFFFFFFFF
FFFFFFFF

std_logic_vector

Comparator status read and fault inject

C_TEST_COMPARATOR

0 = NONE
1 = READ
2 = INJECT

0

integer

Table 4-2: TMR Voter Design Parameters

Feature / Description

Parameter Name

Allowable Values

Default
Value

VHDL
Type

Interface type

C_INTERFACE

0 = Discrete
1 = LMB
2 = BRAM
3 = AXI4
4 = AXI4-Stream Master
5 = AXI4-Stream Slave
6 = ACE
7 = Trace
8 = AXI4-Lite
9 = Interrupt
10 = I/O Bus
11 = GPIO
12 = UART
13 = BRAM Master
14 = LMB Slave
15 = AXI4 Slave
16 = AXI4-Lite Slave
17 = ACE Slave
18 = Interrupt Slave
19 = IIC

0

integer

Activate TMR Disable input

C_USE_TMR_DISABLE

0 = false, 1 = true

0

integer

TMR or Lockstep

C_TMR

0 = Lockstep, 1 = TMR

1

integer

Enable built-in comparator

C_COMPARATOR

0 = false, 1 = true

0

integer

Enable self-checking voter

C_VOTER_CHECK

0 = false, 1 = true

0

integer

Include comparison mask

C_INCLUDE_MASK

Any

0xFFFFFFFF
FFFFFFFF

std_logic_vector

Temporal Lockstep Parameters

First Interface Temporal Depth

C_TEMPORAL_DEPTH1

0 = off, 1 - 31

0

integer

Second Interface Temporal Depth

C_TEMPORAL_DEPTH2

0 = off, 1 - 31

0

integer

Test Parameters

Comparator status read and fault inject

C_TEST_COMPARATOR

0 = NONE
1 = READ
2 = INJECT

0

integer

Last compare status read interface

C_TEST_LAST_INTERFACE

0 = false, 1 = true

0

integer

Status read data width

C_TEST_AXIS_DATA_WIDTH

32

32

integer

Interface Parameters (C_INTERFACE dependent)

Discrete interface width

C_DISCRETE_WIDTH

>0

1

integer

LMB, S_LMB address width

C_LMB_AWIDTH

32 - 64

32

integer

LMB, S_LMB data width

C_LMB_DWIDTH

32

32

integer

LMB, S_LMB has ECC

C_ECC

0 = false, 1 = true

0

integer

AXI4, ACE ID width

C_AXI_ID_WIDTH

>0

1

integer

AXI4, ACE data width

C_AXI_DATA_WIDTH

32,64,128,256,512,1024

32

integer

AXI4, ACE address width

C_AXI_ADDR_WIDTH

32 - 64

32

integer

AXI4, ACE address width

C_AXI_AWUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_ARUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_WUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_RUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_BUSER_WIDTH

>0

1

integer

AXI4-Stream data width

C_AXIS_DATA_WIDTH

8 - 512

32

integer

AXI4-Stream ID width

C_AXIS_ID_WIDTH

1 - 32

1

integer

AXI4-Stream dest width

C_AXIS_DEST_WIDTH

1 - 32

1

integer

AXI4-Stream user width

C_AXIS_USER_WIDTH

1 - 4096

1

integer

Interrupt low latency

C_LOW_LATENCY

0 = false, 1 = true

0

integer

GPIO interface output use

C_USE_GPO

0 = None
1 = Output
2 = Tristate

2

integer

GPIO interface output size

C_GPO_SIZE

32

integer

GPIO interface input use

C_USE_GPI

0 = None, 1 = Input

1

integer

GPIO interface input size

C_GPI_SIZE

32

integer

Table 4-3: TMR Comparator Design Parameters

Feature / Description

Parameter Name

Allowable Values

Default
Value

VHDL
Type

Interface type

C_INTERFACE

0 = Discrete
1 = LMB
2 = BRAM
3 = AXI4
4 = AXI4-Stream Master
5 = AXI4-Stream Slave
6 = ACE
7 = Trace
8 = AXI4-Lite
9 = Interrupt
10 = I/O Bus
11 = GPIO
12 = UART
13 = BRAM Master
14 = LMB Slave
15 = AXI4 Slave
16 = AXI4-Lite Slave
17 = ACE Slave
18 = Interrupt Slave
19 = IIC

0

integer

Activate TMR Disable input

C_USE_TMR_DISABLE

0 = false, 1 = true

0

integer

TMR or Lockstep

C_TMR

0 = Lockstep, 1 = TMR

1

integer

Enable self-checking voter

C_VOTER_CHECK

0 = false, 1 = true

0

integer

Input Register

C_INPUT_REGISTER

0 = false, 1 = true

0

integer

Include comparison mask

C_INCLUDE_MASK

Any

0xFFFFFFFF
FFFFFFFF

integer

Temporal Lockstep Parameters

First Interface Temporal Depth

C_TEMPORAL_DEPTH1

0 = off, 1 - 31

0

integer

Second Interface Temporal Depth

C_TEMPORAL_DEPTH2

0 = off, 1 - 31

0

integer

Test Parameters

Comparator status read and fault inject

C_TEST_COMPARATOR

0 = NONE
1 = READ
2 = INJECT

0

integer

Last compare status read interface

C_TEST_LAST_
INTERFACE

0 = false, 1 = true

0

integer

Status read data width

C_TEST_AXIS_DATA_
WIDTH

32

32

integer

Interface Parameters (C_INTERFACE dependent)

Discrete interface width

C_DISCRETE_WIDTH

>0

1

integer

LMB, S_LMB address width

C_LMB_AWIDTH

32 - 64

32

integer

LMB, S_LMB data width

C_LMB_DWIDTH

32

32

integer

LMB, S_LMB has ECC

C_ECC

0 = false
1 = true

0

integer

LMB, S_LMB bus interface type

C_LMB1, C_LMB2

0 = Monitor
1 = Slave

0

integer

AXI4, ACE ID width

C_AXI_ID_WIDTH

>0

1

integer

AXI4, ACE data width

C_AXI_DATA_WIDTH

32,64,128,256,512,1024

32

integer

AXI4, ACE address width

C_AXI_ADDR_WIDTH

32 - 64

32

integer

AXI4, ACE address width

C_AXI_AWUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_ARUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_WUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_RUSER_WIDTH

>0

1

integer

AXI4, ACE address width

C_AXI_BUSER_WIDTH

>0

1

integer

AXI4, ACE, bus interface type

C_AXI1, C_AXI2

0 = Monitor
1 = Slave

0

integer

AXI4-Stream data width

C_AXIS_DATA_WIDTH

8 - 512

32

integer

AXI4-Stream ID width

C_AXIS_ID_WIDTH

1 - 32

1

integer

AXI4-Stream dest width

C_AXIS_DEST_WIDTH

1 - 32

1

integer

AXI4-Stream user width

C_AXIS_USER_WIDTH

1 - 4096

1

integer

AXI4-Stream bus interface type

C_AXIS1, C_AXIS2

0 = Monitor
1 = Slave

0

integer

Trace interface data size

C_DATA_SIZE

32

32

integer

Trace size

C_TRACE_SIZE

0 = Full
1 = RegWr
2 = RegWr Data

0

integer

Trace bus interface type

C_TRACE
C_TRACE n (n = 1-3)

0 = Monitor
1 = Slave

0

integer

Interrupt low latency

C_LOW_LATENCY

0 = false, 1 = true

0

integer

Interrupt bus interface type

C_IRQ1, C_IRQ2

0 = Monitor
1 = Slave

0

integer

I/O bus interface type

C_IO1, C_IO2

0 = Monitor
1 = Slave

0

integer

UART bus interface type

C_UART1, C_UART2

0 = Monitor
1 = Slave

0

integer

GPIO interface output use

C_USE_GPO

0 = None
1 = Output
2 = Tristate

2

integer

GPIO interface output size

C_GPO_SIZE

32

integer

GPIO interface input use

C_USE_GPI

0 = None, 1 = Input

1

integer

GPIO interface input size

C_GPI_SIZE

32

integer

GPIO bus interface type

C_GPIO1, C_GPIO2

0 = Monitor
1 = Slave

0

integer

Table 4-4: TMR Inject Design Parameters

Feature / Description

Parameter Name

Allowable Values

Default
Value

VHDL
Type

LMB Parameters

TMR Inject base address

C_BASEADDR

Valid address range

0xFFFFFFFF
FFFFFFFF

std_logic_vector

TMR Inject high address

C_HIGHADDR

Valid address range

0x00000000
00000000

std_logic_vector

LMB Decode Mask

C_MASK

Valid decode mask for LMB

0x00000000
00800000

std_logic_vector

LMB address width

C_LMB_AWIDTH

32 - 64

32

integer

LMB data width

C_LMB_DWIDTH

32

32

integer

MB_LMB and BRAM_LMB address width

C_INJECT_LMB_AWIDTH

32 - 64

32

integer

MB_LMB and BRAM_LMB data width

C_INJECT_LMB_DWIDTH

32

32

integer

TMR Parameters

Magic Byte

C_MAGIC

0x00 - 0xFF

0x00

std_logic_vector

CPU Identifier

C_CPU_ID

1 = CPU number 1
2 = CPU number 2
3 = CPU number 3

1

integer

Table 4-5: TMR SEM Design Parameters

Feature / Description

Parameter Name

Allowable Values

Default
Value

VHDL
Type

Selected interface

C_INTERFACE

0 = AXI
1 = UART

0

integer

Output SEM status

C_SEM_STATUS

0 = false, 1 = true

0

integer

SEM interface type

C_SEM_INTERFACE_TYPE

0 = Unknown
1 = 7 Series
2 = UltraScale
3 = UltraScale+

0

integer

SEM monitor line ending

C_LINE_ENDING

0 = CRLF
1 = CR
2 = LF

0

integer

Controller clock frequency

C_S_AXI_ACLK_FREQ_HZ

Any valid frequency

100000000

integer

AXI4-Lite Parameters (C_INTERFACE = 0)

AXI slave address width

C_S_AXI_ADDR_WIDTH

4

4

integer

AXI slave data width

C_S_AXI_DATA_WIDTH

32

32

integer

UART Parameters (C_INTERFACE = 1)

Defines baud rate

C_UART_BAUDRATE

110, 300, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 128000, 230400, 460800, 921600

9600

integer

Use parity

C_USE_UART_PARITY

0 = false, 1 = true

0

integer

Even or odd parity

C_UART_ODD_PARITY

0 = Even
1 = Odd

0

integer

SEM Controller Parameters

Enable injection (1)

ENABLE_INJECTION

false, true

true

Boolean

Enable correction (1)

ENABLE_CORRECTION

false, true

true

Boolean

Correction method (1)

CORRECTION_METHOD

repair,
enhanced repair

enhanced repair

string

Mode (2)

MODE

mitigation and testing, mitigation only, detect and testing, detect only, emulation, monitoring

mitigation and testing

string

Notes:

1. Only available when C_SEM_INTERFACE_TYPE is set to 1.

2. Only available when C_SEM_INTERFACE_TYPE is set to 2 or 3.

The relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl Console) are shown in Table: TMR Manager Design Parameters to Table: TMR SEM Design Parameters . The Vivado IDE parameter is defined in the Feature/Description column, and the User Parameter is defined in the Parameter Name column.