Monitor Receive Register (MON_RECEIVE) - 1.0 English

MicroBlaze Triple Modular Redundancy (TMR) Subsystem (PG268)

Document ID
PG268
Release Date
2022-04-28
Version
1.0 English

This 32-entry-deep FIFO contains data received from the SEM monitor. The FIFO bit definitions are shown in Table: Monitor Receive Register (MON_RECEIVE) . Reading this register results in reading the data word from the top of the FIFO. When a read request is issued to an empty FIFO, a bus error (SLVERR) is generated and the result is undefined. The register is a read-only register. Issuing a write request to the receive data FIFO does nothing but generates a successful write acknowledgment. Table:  Monitor Receive Register Bit Definitions shows the location for data on the AXI slave interface. The register is only implemented if C_INTERFACE is set to 0.

Table 2-52: Monitor Receive Register (MON_RECEIVE)

Reserved

MON_RX

31

8

7

0

Table 2-53: Monitor Receive Register Bit Definitions

Bits

Name

Access

Reset
Value

Description

31:8

-

R

0

Reserved

7:0

MON_RX

R

0

Monitor Receive Data