The MDIOADDR is a 32-bit read/write register (
This Figure
). This register is used to configure the PHY device address, PHY register address and type of MDIO transaction. The bit definition of this register is shown in
Table: MDIO Address Register (0x07E4)
.
Figure 2-12:
MDIO Address Register
|
X-Ref Target - Figure 2-12
|
Table 2-14:
MDIO Address Register (0x07E4)
|
Bits
|
Name
|
Access
|
Reset Value
|
Description
|
|
31:11
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
10
|
OP
|
Read/Write
|
0
|
Operation Access Type
0 – Write Access
1 – Read Access
|
|
9:5
|
PHYADDR
|
Read/Write
|
0
|
PHY device address
|
|
4:0
|
REGADDR
|
Read/Write
|
0
|
PHY register address
|
