The entire receive frame data from destination address to the end of the CRC is stored in the receive dual port memory area which starts at address 0x1000 . The preamble and start-of-frame fields are not stored in dual port memory. Dual port memory address 0x17FC (Bit[0] on the data bus) is used as a status to indicate the presence of a receive packet that is ready for processing by the software.
Dual port memory address 0x17FC (Bit[3] on the data bus) is the Receive Interrupt enable. This event is a pulse and occurs when the memory has data available. The receive complete interrupt occurs only if this bit and GIE are both set to 1.
When the status bit is 0, the AXI Ethernet Lite MAC monitors the Ethernet for packets with a destination address that matches its Ethernet MAC address or the broadcast address. If a packet satisfies either of these conditions, the packet is received and stored in dual port memory starting at address 0x1000 . When the packet has been received, the AXI Ethernet Lite MAC core verifies the CRC. If the CRC value is correct, the status bit is set. If the CRC bit is incorrect, the status bit is not set and the AXI Ethernet Lite MAC core resumes monitoring the Ethernet bus.
Also, if the AXI Ethernet Lite MAC core receive Runt Frame (frame length less than the 60 Bytes) with a valid CRC, the core does not set the status bit and the interrupt is not generated. When the status bit is set, the AXI Ethernet Lite MAC does not perform any receive operations until the bit has been cleared to 0 by the software, indicating that all of the receive data has been retrieved from the dual port memory.
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X-Ref Target - Figure 3-3 
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