The Frame Check Sequence (FCS) field is 4 bytes in length. The value of the FCS field is calculated over the source address, destination address, length/type, data, and pad fields using a 32-bit CRC defined in paragraph 3.2.8 of [Ref 3] :
G(x) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x 1 + x 0
The CRC bits are placed in the FCS field with the x 31 term in the left most bit of the first byte and the x 0 term is the right most bit of the last byte (that is, the bits of the CRC are transmitted in the order x 31 , x 30 ,..., x 1 , x 0 ).
The AXI Ethernet Lite MAC implementation of the CRC algorithm calculates the CRC value a nibble at a time to coincide with the data size exchanged with the external PHY interface for each transmit and receive clock period. For transmission, this field is always inserted automatically by the AXI Ethernet Lite MAC core and is always retained in the receive packet data.
