Transmit Control Register (Ping)

Transmit Control Register (Ping) - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

Document ID

PG135

Release Date

2021-11-02

Version

3.0 English

The Transmit Control register for the ping buffer is a 32-bit read/write register ( This Figure ). This register is used to enable the global interrupt, internal loopback and to initiate transmit transactions. The bit definition of this register is shown in Table: Transmit Control Register (0x07FC) .

Figure 2-8: Transmit Control Register (Ping)
X-Ref Target - Figure 2-8

Table 2-10: Transmit Control Register (0x07FC)
Bits	Name	Access	Reset value	Description
31:5	Reserved	N/A	N/A	Reserved
4	Loopback ⁽¹⁾	Read/Write	0	Internal loopback enable bit 0 – No internal loopback 1 – Internal loopback enable
3	Interrupt Enable	Read/Write	0	Transmit Interrupt Enable bit 0 – Disable transmit interrupt 1 – Enable transmit interrupt
2	Reserved	N/A	N/A	Reserved
1	Program	Read/Write	0	AXI Ethernet Lite MAC address program bit. Setting this bit and status bit configures the new Ethernet MAC address for the core as described in Ethernet MAC Address .
0	Status	Read/Write	0	Transmit ping buffer status indicator 0 –Transmit ping buffer is ready to accept new frame 1 – Frame transfer is in progress. Setting this bit initiates transmit transaction. When transmit is complete, the AXI Ethernet Lite MAC core clears this bit.
Notes: 1. Internal Loopback is supported only in full duplex operation mode. Write to this bit is only valid when, Internal Loopback is enabled from the Vivado IDE options.