Table: AXI Ethernet Lite Register Map
shows all the
AXI Ethernet Lite MAC
core registers and their addresses.
Tables 2-8
to
2-17
show the bit allocation and reset values of the registers.
Table 2-7:
AXI Ethernet Lite Register Map
Address Offset
|
Register Name
|
Description
|
07E4h
|
MDIOADDR
(1)
|
MDIO address register
|
07E8h
|
MDIOWR
(1)
|
MDIO write data register
|
07ECh
|
MDIORD
(1)
|
MDIO read data register
|
07F0h
|
MDIOCTRL
(1)
|
MDIO control register
|
07F4h
|
TX Ping Length
|
Transmit length register for ping buffer
|
07F8h
|
GIE
|
Global interrupt register
|
07FCh
|
TX Ping Control
|
Transmit control register for ping buffer
|
0FF4h
|
TX Pong Length
(2)
|
Transmit length register for pong buffer
|
0FFCh
|
TX Pong Control
(2)
|
Transmit control register for pong buffer
|
17FCh
|
RX Ping Control
|
Receive control register for ping buffer
|
1FFCh
|
RX Pong Control
(3)
|
Receive control register for pong buffer
|
Notes:
1.
These registers are included only if
Enable MII Management Modul
e is set in the Vivado IDE.
2.
These registers are included only if
Enable Transmit Buffers
is set in the Vivado IDE.
3.
These registers are included only if
Enable Receive Buffers
is set in the Vivado IDE.
|