The Receive Control register for the pong buffer is a 32-bit read/write register (
This Figure
). This register indicates whether there is a new packet in the pong buffer. The bit definition of this register is shown in
Table: Receive Control Register (0x1FFC)
.
Figure 2-11:
Receive Control Register (Pong)
|
X-Ref Target - Figure 2-11
|
Table 2-13:
Receive Control Register (0x1FFC)
|
Bits
|
Name
|
Access
|
Reset value
|
Description
|
|
31:1
|
Reserved
|
N/A
|
N/A
|
Reserved
|
|
0
|
Status
|
Read/Write
|
0
|
Receive status indicator
0 – Receive pong buffer is empty.
AXI Ethernet Lite MAC
can accept new available valid packet.
1 – Indicates presence of receive packet ready for software processing.
When the software reads the packet from the receive pong buffer, the software must clear this bit.
|
