Transmit Control Register (Pong)

Transmit Control Register (Pong) - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

Document ID

PG135

Release Date

2021-11-02

Version

3.0 English

The Transmit Control register for the pong buffer is a 32-bit read/write register ( This Figure ). This register is used for Ethernet MAC address programming and to initiate transmit transaction from the pong buffer. The bit definition of this register is shown in Table: Transmit Control Register (0x0FFC) .

Figure 2-9: Transmit Control Register (Pong)
X-Ref Target - Figure 2-9

Table 2-11: Transmit Control Register (0x0FFC)
Bits	Name	Access	Reset value	Description
31:2	Reserved	N/A	N/A	Reserved
1	Program	Read/Write	0	AXI Ethernet Lite MAC address program bit. Setting this bit and status bit configures the new Ethernet MAC address for the core as described in Ethernet MAC Address .
0	Status	Read/Write	0	Transmit pong buffer status indicator 0 – Transmit pong buffer is ready to accept a new frame 1 – Frame transfer is in progress. Setting this bit initiates transmit transaction. When transmit is complete, the Ethernet Lite Ethernet MAC core clears this bit.