Features - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

Document ID

PG135

Release Date

2021-11-02

Version

3.0 English

• Parameterized AXI4 slave interface based on the AXI4 or AXI4-Lite specification for transmit and receive data dual port memory access

• Media Independent Interface (MII) for connection to external 10/100 Mb/s PHY transceivers

• Independent internal 2K byte TX and RX dual port memory for holding data for one packet

• Optional dual buffer memories, 4K byte ping-pong, for TX and RX

• Receive and Transmit Interrupts support

• Optional Management Data Input/Output (MDIO) interface for PHY access

• Internal loopback support

LogiCORE IP Facts Table
Core Specifics
Supported Devices ⁽¹⁾	Versal ^® ACAP, UltraScale+™ Families, UltraScale™ Architecture, Zynq ^® -7000 SoC, 7 Series
Supported User Interfaces	AXI4/AXI4-Lite
Resources	See Table: Resource Estimations for Virtex-7 FPGAs , Table: Resource Estimations for Kintex-7 FPGAs , and Table: Resource Estimations for Artix-7 FPGAs
Provided with Core
Design Files	Encrypted RTL
Example Design	VHDL
Test Bench	VHDL
Constraints File	XDC
Simulation Model	Not Provided
Supported S/W Driver ⁽²⁾	Standalone and Linux
Tested Design Flows ⁽³⁾
Design Entry	Vivado® Design Suite Vivado
Simulation	For supported simulators, see the Xilinx Design Tools: Release Notes Guide .
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 54389
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Xilinx Support web page
Notes: 1. For a complete list of supported devices, see the Vivado IP catalog. 2. Standalone driver details can be found in the SDK directory (<install_directory>/SDK/<release>/data/embeddedsw/doc/xilinx_drivers.htm). Linux OS and driver support information is available from the Xilinx Wiki page . 3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide .