Transmit Length Register - 3.0 English

AXI Ethernet Lite MAC LogiCORE IP Product Guide (PG135)

Document ID
PG135
Release Date
2021-11-02
Version
3.0 English

The Transmit Length register is a 32-bit read/write register ( This Figure ). This register is used to store the length (in bytes) of the transmit data stored in dual port memory. The higher 8 bits of the length value should be stored in data bits 15 to 8, while the lower 8 bits should be stored in data bits 7 to 0. The bit definition of this register for the ping and pong buffer interface is shown in Table: Transmit Length Register (0x07F4),(0x0FF4) .

Figure 2-6: Transmit Length Register

X-Ref Target - Figure 2-6

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Table 2-8: Transmit Length Register (0x07F4),(0x0FF4)

Bits

Name

Access

Reset value

Description

31:16

Reserved

N/A

N/A

Reserved

15:8

MSB

Read/Write

0

The higher 8 bits of the frame length

7:0

LSB

Read/Write

0

The lower 8 bits of the frame length