Creating Pblocks for UltraScale and UltraScale+ Devices - 2021.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
UG909
Release Date
2022-02-25
Version
2021.2 English

As part of improvements to the UltraScale architecture, the smallest unit that can be reconfigured is much smaller than in previous architectures. The minimum required resources for reconfiguration varies based on the resource type, and are referred to as a Programmable Unit (PU). Because adjacent sites share a routing resource (or Interconnect Tile) in UltraScale, a PU is defined in terms of pairs.

Examples of some of the minimum PU that can be reconfigured based on the site types include:

  • CLB PU: 2 adjacent CLBs and the shared interconnect
  • Block RAM PU: 1 block RAM/FIFO, the 5 adjacent CLBs and the shared interconnect
  • DSP PU: 1 DSP, the 5 adjacent CLBs, and the shared interconnect
  • IOB PU: The IO of the full height of the clock_region includes BITSLICE_CONTROL, BITSLICE_RX_TX, BITSLICE_TX, BUFGCE, BUFGCE_DIV, BUFGCTRL, IOB, MMCME3_ADV, PLLE3_ADV, PLL_SELECT_SITE, RIU_OR, HBM_REFCLK etc., the adjacent 60 CLBs and the shared interconnect
  • GT PU: A full GT quad (4 GT_CHANNEL and 1 GT_COMMON), the adjacent 60 CLBs and the shared interconnect
  • PCIe PU: 1 PCIE40E4 or PCIE4CE4, 120 adjacent CLBs (60 on each side) and the shared interconnect
  • CMAC PU: 1 CMACE4, 120 adjacent CLBs (60 on each side) and the shared interconnect
  • Interlaken PU: 1 ILKNE4, 120 adjacent CLBs (60 on each side) and the shared interconnect
  • CONFIG PU: 1 CONFIG_SITE, 120 adjacent CLBs (60 on each side) and the shared interconnect
    • Note: The CONFIG_SITE contains many single site resources including ICAP, STARTUP, BSCAN, FRAME_ECC, DNA_PORT, EFUSE_USR and MASTER_JTAG, and cannot be broken up further.
  • HBM BLI PU: 1 HBM_PLI, 15 adjacent CLBs and the shared interconnect.