Clocking - 2.0 English

SMPTE UHD-SDI RX Subsystem (PG290)

Document ID
PG290
Release Date
2023-05-17
Version
2.0 English

QPLL0 is allocated for UHD-SDI RX transceiver and QPLL1 for UHD-SDI TX in this pass-through design. The reference clock for QPLL1 comes from si5328 chip output. Thus, QPLL1 reference clock connection is fixed. QPLL0 reference clock is fixed to 148.5 MHz which comes from on-board si570 chip. This Figure shows the clocking used in the UHD-SDI example design.

Figure 5-24: ZCU106 Audio-Video Pass-Through Example Design Clocking

X-Ref Target - Figure 5-24

X21406-pg290-zcu106-pass-thru-ex-des.jpg

Table: ZCU106 Pass-Through Example Design Clock Frequency Ranges shows the clock frequency at different part of the system for different SDI modes:

Table 5-4: ZCU106 Audio-Video Example Design Clock Frequency Ranges

SDI Mode

Tx_m/

Rx_m

QPLL0
Ref clk
(MHz)

QPLL1
Ref Clk
(MHz)

txoutclk
(MHz)

si5328
Input
(MHz)

si5328
Output
(MHz)

txoutclk
(MHz)

SD-SDI

N/A

148.5

148.5

148.5
rx_sd_ce=27

rx_sd_ce=27

148.5

148.5

HD-SDI

0

148.5

148.5

74.25

74.25

148.5

74.25

HD-SDI

1

148.5

148.5/1.001

74.25/1.001

74.25/1.001

148.5/1.001

74.25/1.001

3G-SDI/6G-SDI

0

148.5

148.5

148.5

148.5

148.5

148.5

3G-SDI/6G-SDI

1

148.5

148.5/1.001

148.5/1.001

148.5/1.001

148.5/1.001

148.5/1.001

12G-SDI

0

148.5

148.5

297

297

148.5

297

12G-SDI

1

148.5

148.5/1.001

297/1.001

297/1.001

148.5/1.001

297/1.001

Note: For 6G-SDI and 12G-SDI, 8 native SDI Data Streams (DS) is assumed.

For GT TX and RX data path, the reference clock requirement for data paths are different. For GT TX, for integer and fractional frame rate, PLL reference clock must be different frequency, clock/1.000 for integer frame rate and clock/1.001 for fractional frame rate. For RX data path PLL reference clock can be same for integer and fractional frame rate up to 6-G SDI and separate reference clock is required for 12-G SDI integer and fractional frame rate.