Configure the HDL Blocks - 2022.1 English

This allows you to review the properties of the existing filter.

• Frequency Specifications
  • Units = MHz
  • Fs = 20
  • Fpass = 1.5
  • Fstop = 8.5

• Magnitude Specifications
  • Units = dB
  • Apass = 0.01
  • Astop = 100

Now, associate the filter parameters of the FDATool instance with the Digital FIR Filter instance.

In an FPGA, the design operates at a specific clock rate and using a specific number of bits to represent the data values.

The transition between the continuous time used in the standard Simulink environment and the discrete time of the FPGA hardware environment is determined by defining the sample rate of the Gateway In blocks. This determines how often the continuous input waveform is sampled. This sample rate is automatically propagated to other blocks in the design by Vitis Model Composer. In a similar manner, the number of bits used to represent the data is defined in the Gateway In block and also propagated through the system.

Although not used in this tutorial, some HDL blocks enable rate changes and bit-width changes, up or down, as part of this automatic propagation. More details on these blocks are found in the Vitis Model Composer User Guide (UG1483).

Both of these attributes (rate and bit width) determine the degree of accuracy with which the continuous time signal is represented. Both of these attributes also have an impact on the size, performance, and hence cost of the final hardware.

Vitis Model Composer allows you to use the Simulink environment to define, simulate, and review the impact of these attributes.

Because the highest frequency sine wave in the design is 9 MHz, sampling theory dictates the sampling frequency of the input port must be at least 18 MHz. For this design, you will use 20 MHz.

This now allows us to use accurate sample rate and bit-widths to accurately verify the hardware.

Because the input port is sampled at 20 MHz to adequately represent the data, you must define the clock rate of the FPGA and the Simulink sample period to be at least 20 MHz.

1. Specify an FPGA clock period of 50 ns (1/20 MHz).
2. Specify a Simulink system period of 1/20e6 seconds.
3. From the Perform analysis menu, select Post Synthesis and from the Analyzer type menu select Resource as shown in the following figure. This option gives the resource utilization details after completion.
   
   

Because the new design is cycle and bit accurate, simulation might take longer to complete than before.

The results are shown above, on the right hand side (in the Spectrum Analyzer HDL window), and differ slightly from the original design (shown on the left in the Spectrum Analyzer FDA Tool window). This is due to the quantization and sampling effect inherent when a continuous time system is described in discrete time hardware.

The final step is to implement this design in hardware. This process will synthesize everything contained between the Gateway In and Gateway Out blocks into a hardware description. This description of the design is output in the Verilog or VHDL Hardware Description Language (HDL). This process is controlled by the System Generator token.

The compilation process transforms the design captured in Simulink blocks into an industry standard Register Transfer Level (RTL) design description. The RTL design can be synthesized into a hardware design. A Resource Analyzer window appears when the hardware design description has been generated.