XPHY - 2022.1 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2022-04-20
Version
2022.1 English

Primitive: XPHY Logic

  • PRIMITIVE_GROUP: I/O
  • PRIMITIVE_SUBGROUP: BITSLICE

Introduction

The XPHY is the hardened XPHY Logic I/O block in Versal devices for Advanced IO Interfaces and Memory Controller IP. This element is not intended to be instantiated, used, or modified outside of Xilinx-generated IP.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog Yes

Related Information

  • Versal ACAP SelectIO Resources Architecture Manual (AM010)