Primitive Groups - 2022.1 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2022-04-20
Version
2022.1 English

The following Primitive Groups correlate to the PRIMTIVE_GROUP cell property in the Vivado software. Similarly, the listed Primitive Subgroup correlates to the PRIMTIVE_SUBGROUP property on the cells in the software. These can be used in filters to specify a class of cells for constraint processing and other tasks within Vivado.

ADVANCED

Design Element Description Primitive Subgroup
DDRMC Primitive: DDR4 memory controller BUFFER
DDRMC_RIU Primitive: DDR4 memory controller Register Interface Unit BUFFER
GTYE5_QUAD Primitive: Gigabit Transceiver for Versal devices GT
IBUFDS_GTE5 Primitive: Gigabit Transceiver Buffer GT
MRMAC Primitive: Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) MAC
NOC_NCRB Primitive: NoC Clock Reconvergent Buffer BUFFER
NOC_NMU128 Primitive: NoC Master Unit BUFFER
NOC_NMU512 Primitive: NoC Master Unit BUFFER
NOC_NPS5555 Primitive: NoC Packet Switch BUFFER
NOC_NPS_VNOC Primitive: NoC Packet Switch BUFFER
NOC_NSU128 Primitive: NoC Slave Unit BUFFER
NOC_NSU512 Primitive: Noc Slave Unit BUFFER
NPI_NIR Primitive: NoC Peripheral Interface BUFFER
OBUFDS_GTE5 Primitive: Gigabit Transceiver Buffer GT
OBUFDS_GTE5_ADV Primitive: Gigabit Transceiver Buffer GT
PCIE40E5 Primitive: Integrated block for PCI Express. PCIE

ARITHMETIC

Design Element Description Primitive Subgroup
DSP58 Primitive: 58-bit Multi-Functional Arithmetic Block DSP
DSPCPLX Primitive: 18 x 18 + 58 complex multiply accumulate block DSP
DSPFP32 Primitive: The DSPFP32 consists of a floating-point multiplier and a floating-point adder with separate outputs. DSP

BLOCKRAM

Design Element Description Primitive Subgroup
RAMB18E5 Primitive: 18K-bit Configurable Synchronous Block RAM BRAM
RAMB36E5 Primitive: 36K-bit Configurable Synchronous Block RAM BRAM
URAM288E5 Primitive: 288K-bit High-Density Memory Building Block URAM
URAM288E5_BASE Primitive: 288K-bit High-Density Base Memory Building Block URAM

CLB

Design Element Description Primitive Subgroup
LUT6_2 Primitive: Six-input, 2-output, Look-Up Table LUT
RAM128X1D Primitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM) LUTRAM
RAM128X1S Primitive: 128-Deep by 1-Wide Random Access Memory (Select RAM) LUTRAM
RAM256X1D Primitive: 256-Deep by 1-Wide Dual Port Random Access Memory (Select RAM) LUTRAM
RAM256X1S Primitive: 256-Deep by 1-Wide Random Access Memory (Select RAM) LUTRAM
RAM32M Primitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM) LUTRAM
RAM32M16 Primitive: 32-Deep by 16-bit Wide Multi Port Random Access Memory (Select RAM) LUTRAM
RAM32X1D Primitive: 32-Deep by 1-Wide Static Dual Port Synchronous RAM LUTRAM
RAM32X1S Primitive: 32-Deep by 1-Wide Static Synchronous RAM LUTRAM
RAM512X1S Primitive: 512-Deep by 1-Wide Random Access Memory (Select RAM) LUTRAM
RAM64M Primitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) LUTRAM
RAM64M8 Primitive: 64-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM) LUTRAM
RAM64X1D Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAM LUTRAM
RAM64X1S Primitive: 64-Deep by 1-Wide Static Synchronous RAM LUTRAM
AND2B1L Primitive: Two input AND gate implemented in place of a CLB Latch LATCH
CFGLUT5 Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT) LUT
LOOKAHEAD8 Primitive: Carry Look-Ahead Multiplexer CARRY
LUT1 Primitive: 1-Bit Look-Up Table LUT
LUT2 Primitive: 2-Bit Look-Up Table LUT
LUT3 Primitive: 3-Bit Look-Up Table LUT
LUT4 Primitive: 4-Bit Look-Up Table LUT
LUT5 Primitive: 5-Bit Look-Up Table LUT
LUT6 Primitive: 6-Bit Look-Up Table LUT
LUT6CY Primitive: 6-Bit Look-Up Table with Carry LUT
OR2L Primitive: Two input OR gate implemented in place of a CLB Latch LATCH
RAM32X16DR8 Primitive: Asymmetric LUTRAM LUTRAM
RAM64X8SW Primitive: 64-Deep by 8-bit Wide Random Access Memory with Single-Bit Write (Select RAM) LUTRAM
SRL16E Primitive: 16-Bit Shift Register Look-Up Table (LUT) SRL
SRLC32E Primitive: 32-Bit Shift Register Look-Up Table (LUT) SRL

CLOCK

Design Element Description Primitive Subgroup
BUFG Primitive: General Clock Buffer BUFFER
BUFG_FABRIC Primitive: Global Clock Buffer driven by fabric interconnect BUFFER
BUFG_GT Primitive: Clock Buffer Driven by Gigabit Transceiver BUFFER
BUFG_GT_SYNC Primitive: Synchronizer for BUFG_GT Control Signals CLOCK_SYNC
BUFG_PS Primitive: A high-fanout buffer for low-skew distribution of the PS Clock signals BUFFER
BUFGCE Primitive: General Clock Buffer with Clock Enable BUFFER
BUFGCE_1 Primitive: General Clock Buffer with Clock Enable and Output State 1 BUFFER
BUFGCE_DIV Primitive: General Clock Buffer with Divide Function BUFFER
BUFGCTRL Primitive: General Clock Control Buffer MUX
BUFGMUX Primitive: General Clock Mux Buffer MUX
BUFGMUX_1 Primitive: General Clock Mux Buffer with Output State 1 MUX
BUFGMUX_CTRL Primitive: 2-to-1 General Clock MUX Buffer MUX
DPLL Primitive: Digital Phase-Locked Loop (DPLL) PLL
MBUFG_GT Primitive: Multi-Output Clock Buffer Driven by Gigabit Transceiver BUFFER
MBUFG_PS Primitive: A Multi-Output high-fanout buffer for low-skew distribution of the PS Clock signals BUFFER
MBUFGCE Primitive: Multi-Output Global Clock Buffer with Enable BUFFER
MBUFGCE_DIV Primitive: Multi-Output Clock Buffer with an enable and divide function BUFFER
MBUFGCTRL Primitive: Multi-Output Global Clock Control Buffer MUX
MMCME5 Primitive: Mixed Mode Clock Manager (MMCM) PLL
XPLL Primitive: XPIO PLL PLL

I/O

Design Element Description Primitive Subgroup
IBUF Primitive: Input Buffer INPUT_BUFFER
IBUF_IBUFDISABLE Primitive: Input Buffer With Input Buffer Disable INPUT_BUFFER
IBUF_INTERMDISABLE Primitive: Input Buffer With Input Buffer Disable and On-die Input Termination Disable INPUT_BUFFER
IBUFDS Primitive: Differential Input Buffer INPUT_BUFFER
IBUFDS_DIFF_OUT Primitive: Differential Input Buffer With Complementary Outputs INPUT_BUFFER
IBUFDS_DIFF_OUT _IBUFDISABLE Primitive: Differential Input Buffer With Complementary Outputs and Input Buffer Disable INPUT_BUFFER
IBUFDS_DIFF_OUT _INTERMDISABLE Primitive: Differential Input Buffer with Complementary Outputs, Input Path Disable and On-die Input Termination Disable INPUT_BUFFER
IBUFDS_DPHY Primitive: Differential Input Buffer with MIPI support INPUT_BUFFER
IBUFDS_IBUFDISABLE Primitive: Differential Input Buffer With Input Buffer Disable INPUT_BUFFER
IBUFDS_INTERMDISABLE Primitive: Differential Input Buffer With Input Buffer Disable and On-die Input Termination Disable INPUT_BUFFER
IBUFDSE3 Primitive: Differential Input Buffer with Offset Calibration INPUT_BUFFER
IBUFE3 Primitive: Input Buffer with Offset Calibration and VREF Tuning INPUT_BUFFER
IDELAYE5 Primitive: Input Delay Element DELAY
IOBUF Primitive: Input/Output Buffer BIDIR_BUFFER
IOBUF_DCIEN Primitive: Input/Output Buffer DCI Enable BIDIR_BUFFER
IOBUF_INTERMDISABLE Primitive: Bidirectional Buffer with Input Path Disable and On-die Input Termination Disable BIDIR_BUFFER
IOBUFDS Primitive: Differential Input/Output Buffer BIDIR_BUFFER
IOBUFDS_DCIEN Primitive: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input Termination Disable BIDIR_BUFFER
IOBUFDS_DIFF_OUT Primitive: Differential Input/Output Buffer Primitive With Complementary Outputs for the Input Buffer BIDIR_BUFFER
IOBUFDS_DIFF_OUT _DCIEN Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Path Disable, and On-die Input Termination Disable BIDIR_BUFFER
IOBUFDS_DIFF_OUT _INTERMDISABLE Primitive: Differential Bidirectional Buffer with Complementary Outputs, Input Buffer Disable and On-die Input Termination Disable BIDIR_BUFFER
IOBUFDS_INTERMDISABLE Primitive: Differential Bidirectional Buffer With Input Buffer Disable and On-die Input BIDIR_BUFFER
IOBUFDSE3 Primitive: Differential Bidirectional I/O Buffer with Offset Calibration BIDIR_BUFFER
IOBUFE3 Primitive: Bidirectional I/O Buffer with Offset Calibration and VREF Tuning BIDIR_BUFFER
KEEPER Primitive: I/O Weak Keeper WEAK_DRIVER
OBUF Primitive: Output Buffer OUTPUT_BUFFER
OBUFDS Primitive: Differential Output Buffer OUTPUT_BUFFER
OBUFDS_DPHY Primitive: Differential Output Buffer with MIPI support OUTPUT_BUFFER
OBUFT Primitive: 3-State Output Buffer OUTPUT_BUFFER
OBUFTDS Primitive: Differential 3-state Output Buffer OUTPUT_BUFFER
ODELAYE5 Primitive: Output Delay Element DELAY
PULLDOWN Primitive: I/O Pulldown WEAK_DRIVER
PULLUP Primitive: I/O Pullup WEAK_DRIVER
XPHY Primitive: XPHY Logic BITSLICE
XPIO_VREF Primitive: VREF Scan INPUT_BUFFER

REGISTER

Design Element Description Primitive Subgroup
FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear SDR
FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset SDR
FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset SDR
FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set SDR
IDDRE1 Primitive: Dedicated Double Data Rate (DDR) Input Register DDR
LDCE Primitive: Transparent Latch with Clock Enable and Asynchronous Clear LATCH
LDPE Primitive: Transparent Latch with Clock Enable and Asynchronous Preset LATCH
ODDRE1 Primitive: Dedicated Double Data Rate (DDR) Output Register DDR