The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter/Value 1 | User Parameter/Value | Default Value |
|---|---|---|
Tx/Rx Protocol Selection
|
C_Tx/Rx_Protocol | HDMI |
| Tx/Rx Max GT Line Rate | Rx_Max_GT_Line_Rate |
|
| Tx/Rx Channels | C_Tx/Rx_No_Of_Channels |
|
TX PLL Type
2
|
C_TX_PLL_SELECTION | LCPLL |
| RX PLL Type
2
(similar to TX PLL Type) |
C_RX_PLL_SELECTION | RPLL |
TX Ref Clock Selection:
2
|
C_TX_REFCLK_SEL | GT REFCLK1 |
| RX Ref Clock Selection
2
(similar to TX Ref Clock Selection) |
C_RX_REFCLK_SEL | GT REFCLK0 |
TX FRL Ref Clock Selection:
|
C_TX_FRL_REFCLK_SEL | GT REFCLK2 |
| RX FRL Ref Clock Selection
2
(similar to TX FRL Ref Clock Selection) |
C_RX_FRL_REFCLK_SEL | GT REFCLK2 |
| TX REFCLK Ready Active | C_Txrefclk_Rdy_Invert | true |
| Use fourth GT Channel as TX TMDS Clock | C_Use_GT_CH4_HDMI |
|
| NI-DRU | C_NIDRU | true |
| NI-DRU Ref Clock Selection (similar to TX Ref Clock Selection) |
C_NIDRU_REFCLK_SEL | GT REFCLK2 |
Number of pixels per clock Value Selection
|
C_INPUT_PIXELS_PER_CLOCK | 4 |
Transceiver Width Value Selection
|
Transceiver_Width | 4 |
| Use ODDR/ODDRE1 for TX and RX differential TMDS clock out | C_Use_Oddr_for_Tmds_Clkout 2 | true |
| TX TMDS Clock output buffer none, bufg 3 |
C_Tx_Tmds_Clk_Buffer 2 | bufg |
|
TX Video Clock output buffer none, bufg 3 |
C_Tx_Video_Clk_Buffer 2 | bufg |
| RX TMDS Clock output buffer none, bufg 3 |
C_Rx_Tmds_Clk_Buffer 2 | bufg |
| RX Video Clock output buffer none, bufg 3 |
C_Rx_Video_Clk_Buffer 2 | bufg |
| DRU Reference Clock Frequency Valid
values
|
C_DRU_Refclk_Freq_MHz | 400.00 |
|
||