•Supports CAUI-10, CAUI-4, 100GAUI-2, 100GAUI-4, and run-time switchable between CAUI-4 and CAUI-10 modes
•512-bit segmented local bus (LBUS) user interface/AXI4-Stream (AXIS) user interface at ~322 MHz
•32-bit interface to the serial transceiver for CAUI-10 lanes, 80-bit interface to the serial transceiver for CAUI-4/100GAUI-4 lanes and 160-bit interface to the serial transceiver for 100GAUI-2 lanes
•IEEE 1588-2008 [Ref 1] one-step and two-step hardware timestamping at ingress and egress at full 80 bits
•Pause frame processing including priority based flow control per IEEE std 802.3-2012 Annex 31 [Ref 2]
•Optional fee-based Auto-Negotiation and Link Training feature for CAUI-4 mode
•Optional built-in 802.3bj-2014 Clause 91 RS-FEC block in CAUI-4 and runtime switch CAUI-4 modes
•Receive side OTN interface
•Optional soft TX OTN interface support
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family(1) |
AMD UltraScale+™ |
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Supported User Interfaces |
Segmented LBUS, AXI4-Stream |
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Resources |
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Provided with Core |
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Design Files |
Verilog |
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Example Design |
Verilog |
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Test Bench |
Verilog |
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Constraints File |
Xilinx Design Constraints (XDC) |
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Simulation Model |
Verilog |
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Supported |
N/A |
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Tested Design Flows(2) |
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Design Entry |
AMD Vivado™ Design Suite |
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Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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Synthesis |
Vivado synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: 67395 |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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