|
Name
|
Type
|
Description
|
Default Value
|
|
LBUS Interface – TX Path Control/Status
|
|
CTL_TX_FCS_INS_ENABLE
|
Boolean
|
Enable FCS insertion by the TX core.
•TRUE: 100G Ethernet IP core calculates and adds FCS to the packet.
•FALSE: 100G Ethernet IP core does not add FCS to the packet.
This attribute cannot be changed dynamically between packets.
|
TRUE
|
|
CTL_TX_IGNORE_FCS
|
Boolean
|
Enable FCS error checking at the LBUS interface by the TX core. This input only has effect when ctl_tx_fcs_ins_enable is FALSE.
•TRUE: A packet with bad FCS transmitted is binned as good.
•FALSE: A packet with bad FCS transmitted is not binned as good.
The error is flagged on the signals stat_tx_bad_fcs and STAT_RX_STOMPED_FCS, and the packet is transmitted as it was received.
Statistics are reported as if there was no FCS error.
|
FALSE
|
|
CTL_TX_IPG_VALUE[3:0]
|
4-bit Hex
|
The ctl_tx_ipg_value defines the target average minimum Inter Packet Gap (IPG, in bytes) inserted between LBUS packets. Valid values are 8 to 12. The ctl_tx_ipg_value can also be programmed to a value in the 0 to 7 range, but in that case, it is interpreted as meaning minimal IPG, so only Terminate code word IPG is inserted; no Idles are ever added in that case - and that produces an average IPG of around 4 bytes when random-size packets are transmitted.
|
4'hC
|
|
CTL_TX_VL_LENGTH_MINUS1[15:0]
|
16-bit Hex
|
Number of words in between PCS Lane markers minus one. Default value, as defined in IEEE 802.3, should be set to 16383 (decimal).
|
16’h3FFF
|
|
CTL_TX_VL_MARKER_ID0[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 0. For IEEE 802.3 default values, see the specification.
|
64'hc16821003e97de00
|
|
CTL_TX_VL_MARKER_ID1[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 1.
|
64’h9d718e00628e7100
|
|
CTL_TX_VL_MARKER_ID2[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 2.
|
64’h594be800a6b41700
|
|
CTL_TX_VL_MARKER_ID3[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 3.
|
64’h4d957b00b26a8400
|
|
CTL_TX_VL_MARKER_ID4[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 4.
|
64’hf50709000af8f600
|
|
CTL_TX_VL_MARKER_ID5[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 5.
|
64’hdd14c20022eb3d00
|
|
CTL_TX_VL_MARKER_ID6[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 6.
|
64’h9a4a260065b5d900
|
|
CTL_TX_VL_MARKER_ID7[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 7.
|
64’h7b45660084ba9900
|
|
CTL_TX_VL_MARKER_ID8[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 8.
|
64’ha02476005fdb8900
|
|
CTL_TX_VL_MARKER_ID9[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 9.
|
64’h68c9fb0097360400
|
|
CTL_TX_VL_MARKER_ID10[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 10.
|
64’hfd6c990002936600
|
|
CTL_TX_VL_MARKER_ID11[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 11.
|
64’hb9915500466eaa00
|
|
CTL_TX_VL_MARKER_ID12[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 12.
|
64’h5cb9b200a3464d00
|
|
CTL_TX_VL_MARKER_ID13[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 13.
|
64’h1af8bd00e5074200
|
|
CTL_TX_VL_MARKER_ID14[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 14.
|
64’h83c7ca007c383500
|
|
CTL_TX_VL_MARKER_ID15[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 15.
|
64’h3536cd00cac93200
|
|
CTL_TX_VL_MARKER_ID16[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 16.
|
64’hc4314c003bceb300
|
|
CTL_TX_VL_MARKER_ID17[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 17.
|
64’hadd6b70052294800
|
|
CTL_TX_VL_MARKER_ID18[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 18.
|
64’h5f662a00a099d500
|
|
CTL_TX_VL_MARKER_ID19[63:0]
|
64-bit Hex
|
This bus sets the TX PCS Lane marker for PCS lane 19.
|
64’hc0f0e5003f0f1a00
|
|
LBUS Interface – RX Path Control/Status Signals
|
|
CTL_RX_CHECK_PREAMBLE
|
Boolean
|
When set to TRUE, this attribute
causes the Ethernet MAC to check the preamble of the received frame.
|
FALSE
|
|
CTL_RX_CHECK_SFD
|
Boolean
|
When set to TRUE, this attribute causes the Ethernet MAC to check the Start of Frame Delimiter of the received frame.
|
FALSE
|
|
CTL_RX_DELETE_FCS
|
Boolean
|
Enable FCS removal by the RX core.
•TRUE: 100G Ethernet IP core deletes the FCS of the incoming packet.
•FALSE: 100G Ethernet IP core does not remove the FCS of the incoming packet.
FCS is not deleted for packets that are less than or equal to 8 bytes long.
|
TRUE
|
|
CTL_RX_IGNORE_FCS
|
Boolean
|
Enable FCS error checking at the LBUS interface by the RX core.
•TRUE: 100G Ethernet IP core does not flag an FCS error at the LBUS interface.
•FALSE: A packet received with an FCS error is sent with the RX_ERROUT pin asserted during the last transfer (RX_EOPOUT and RX_ENAOUT are sampled as 1).
Note: The statistics are reported as if the packet is good. The signal stat_rx_bad_fcs, however, reports the error.
|
FALSE
|
|
CTL_RX_MAX_PACKET_LEN[14:0]
|
15-bit Hex
|
Any packet longer than this value is considered to be oversized. If a packet has a size greater than this value, the packet is truncated to this value and the RX_ERROUT signal is asserted along with the rx_eopout signal. ctl_rx_max_packet_len[14] is reserved and must be set to 0.
Packets less than 64 bytes are dropped. The allowed value for this bus can range from 64 to 16,383.
|
15’h2580
|
|
CTL_RX_MIN_PACKET_LEN[7:0]
|
8-bit Hex
|
Any packet shorter than the default value of 64 (decimal) is considered to be undersized. If a packet has a size less than this value, the rx_errout signal is asserted during the rx_eopout asserted cycle. Packets less than 64 bytes are dropped. The value of this bus must be less than or equal to the value of CTL_RX_MAX_PACKET_LEN[14:0].
|
8’h40
|
|
CTL_RX_VL_LENGTH_MINUS1[15:0]
|
16-bit Hex
|
Number of words in between PCS Lane markers minus one. Default value, as defined in IEEE 802.3, should be set to 16,383 (decimal).
|
16’h3FFF
|
|
CTL_RX_VL_MARKER_ID0[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 0. For IEEE 802.3 default values, see the specification.
|
64’hc16821003e97de00
|
|
CTL_RX_VL_MARKER_ID1[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 1.
|
64’h9d718e00628e7100
|
|
CTL_RX_VL_MARKER_ID2[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 2.
|
64’h594be800a6b41700
|
|
CTL_RX_VL_MARKER_ID3[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 3.
|
64’h4d957b00b26a8400
|
|
CTL_RX_VL_MARKER_ID4[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 4.
|
64’hf50709000af8f600
|
|
CTL_RX_VL_MARKER_ID5[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 5.
|
64’hdd14c20022eb3d00
|
|
CTL_RX_VL_MARKER_ID6[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 6.
|
64’h9a4a260065b5d900
|
|
CTL_RX_VL_MARKER_ID7[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 7.
|
64’h7b45660084ba9900
|
|
CTL_RX_VL_MARKER_ID8[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 8.
|
64’ha02476005fdb8900
|
|
CTL_RX_VL_MARKER_ID9[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 9.
|
64’h68c9fb0097360400
|
|
CTL_RX_VL_MARKER_ID10[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 10.
|
64’hfd6c990002936600
|
|
CTL_RX_VL_MARKER_ID11[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 11.
|
64’hb9915500466eaa00
|
|
CTL_RX_VL_MARKER_ID12[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 12.
|
64’h5cb9b200a3464d00
|
|
CTL_RX_VL_MARKER_ID13[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 13.
|
64’h1af8bd00e5074200
|
|
CTL_RX_VL_MARKER_ID14[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 14.
|
64’h83c7ca007c383500
|
|
CTL_RX_VL_MARKER_ID15[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 15.
|
64’h3536cd00cac93200
|
|
CTL_RX_VL_MARKER_ID16[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 16.
|
64’hc4314c003bceb300
|
|
CTL_RX_VL_MARKER_ID17[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 17.
|
64’hadd6b70052294800
|
|
CTL_RX_VL_MARKER_ID18[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 18.
|
64’h5f662a00a099d500
|
|
CTL_RX_VL_MARKER_ID19[63:0]
|
64-bit Hex
|
This bus sets the RX PCS Lane marker for PCS lane 19.
|
64’hc0f0e5003f0f1a00
|
|
Miscellaneous Status/Control
|
|
CTL_RX_PROCESS_LFI
|
Boolean
|
TRUE: The 100G Ethernet IP core RX core will expect and process LF control codes coming in from the SerDes.
FALSE: The 100G Ethernet IP core RX core ignores LFI control codes coming in from the SerDes.
Note: If an LFI condition is detected, the core will stop receiving packets until the LFI is cleared. Packets in progress will be terminated and an error will be indicated on the LBUS. A START block must be received before packets are received again.
|
FALSE
|
|
Pause Interface – RX Path
|
|
CTL_RX_PAUSE_DA_UCAST[47:0]
|
48-bit Hex
|
Unicast destination address for pause processing.
|
48'h000000000000
|
|
CTL_RX_PAUSE_SA[47:0]
|
48-bit Hex
|
Source address for pause processing.
|
48'h000000000000
|
|
CTL_RX_OPCODE_MIN_GCP[15:0]
|
16-bit Hex
|
Minimum global control opcode value.
|
16’h0000
|
|
CTL_RX_OPCODE_MAX_GCP[15:0]
|
16-bit Hex
|
Maximum global control opcode value.
|
16’hffff
|
|
CTL_RX_ETYPE_GCP[15:0]
|
16-bit Hex
|
Ethertype field for global control processing.
|
16’h8808
|
|
CTL_RX_PAUSE_DA_MCAST[47:0]
|
48-bit Hex
|
Multicast destination address for pause processing.
|
48’h0180c2000001
|
|
CTL_RX_ETYPE_PCP[15:0]
|
16-bit Hex
|
Ethertype field for priority control processing.
|
16’h8808
|
|
CTL_RX_OPCODE_MIN_PCP[15:0]
|
16-bit Hex
|
Minimum priority control opcode value.
|
16’h0000
|
|
CTL_RX_OPCODE_MAX_PCP[15:0]
|
16-bit Hex
|
Maximum priority control opcode value.
|
16’hffff
|
|
CTL_RX_ETYPE_GPP[15:0]
|
16-bit Hex
|
Ethertype field for global pause processing.
|
16’h8808
|
|
CTL_RX_OPCODE_GPP[15:0]
|
16-bit Hex
|
Global pause opcode value.
|
16’h0001
|
|
CTL_RX_ETYPE_PPP[15:0]
|
16-bit Hex
|
Ethertype field for priority pause processing.
|
16’h8808
|
|
CTL_RX_OPCODE_PPP[15:0]
|
16-bit Hex
|
Priority pause opcode value.
|
16'h0101
|
|
CTL_RX_CHECK_ACK
|
Boolean
|
Wait for acknowledge.
•TRUE: 100G Ethernet IP core uses the CTL_RX_PAUSE_ACK[8:0] bus for pause processing.
•FALSE: CTL_RX_PAUSE_ACK[8:0] is not used.
|
TRUE
|
|
CTL_RX_FORWARD_CONTROL
|
Boolean
|
TRUE: 100G Ethernet IP core will forward control packets.
FALSE: 100G Ethernet IP core will drop control packets.
See Pause Processing Interface.
|
FALSE
|
|
Pause Interface – TX Path
|
|
CTL_TX_DA_GPP[47:0]
|
48-bit Hex
|
Destination address for transmitting global pause packets.
|
48’h0180c2000001
|
|
CTL_TX_SA_GPP[47:0]
|
48-bit Hex
|
Source address for transmitting global pause packets.
|
48’h000000000000
|
|
CTL_TX_ETHERTYPE_GPP[15:0]
|
16-bit Hex
|
Ethertype for transmitting global pause packets.
|
16’h8808
|
|
CTL_TX_OPCODE_GPP[15:0]
|
16-bit Hex
|
Opcode for transmitting global pause packets.
|
16’h0001
|
|
CTL_TX_DA_PPP[47:0]
|
48-bit Hex
|
Destination address for transmitting priority pause packets.
|
48’h0180c2000001
|
|
CTL_TX_SA_PPP[47:0]
|
48-bit Hex
|
Source address for transmitting priority pause packets.
|
48’h000000000000
|
|
CTL_TX_ETHERTYPE_PPP[15:0]
|
16-bit Hex
|
Ethertype for transmitting priority pause packets.
|
16’h8808
|
|
CTL_TX_OPCODE_PPP[15:0]
|
16-bit Hex
|
Opcode for transmitting priority pause packets.
|
16'h0101
|
|
IEEE 1588 Interface – TX Path
|
|
CTL_TX_PTP_1STEP_ENABLE
|
Boolean
|
FALSE: Disable 1-step operation.
|
FALSE
|
|
CTL_PTP_TRANSPCLK_MODE
|
Boolean
|
This attribute, when set to TRUE, places the timestamping logic into transparent clock mode and enables correction field updates on the TX. In transparent clock mode, the system timer input is interpreted as the correction value. The TX will calculate the correction field value and overwrite the original value.
Note: Both RX and TX timer inputs are expected to be in correction field format as well as timestamps.
|
FALSE
|
|
CTL_TX_PTP_LATENCY_ADJUST[10:0]
|
11’bit Hex
|
This bus can be used to adjust the 1-step TX timestamp with respect to the 2-step timestamp. The units of the bus bits [10:3] are nanoseconds. The 3 LSB bits in this input are fractional nanoseconds.
In normal mode, the usual value is 705 decimal (2C1 hex), corresponding to the delay between the 1-step logic and the 2-step timestamp capture plane.
In transparent clock mode, the value of 802 decimal (322 hex) is recommended.
|
11’h2C1
|
|
CTL_RX_RSFEC_FILL_ADJUST[1:0]
|
2-bit Hex
|
Reserved. Must be set to 2'h0.
|
2'h0
|
|
CTL_RX_RSFEC_AM_THRESHOLD[8:0]
|
9'bit Hex
|
Reserved. Must be set to 9'h46.
|
9'h46
|
|
CTL_TX_CUSTOM_PREAMBLE
|
Boolean
|
Enable/disable the custom preamble feature.
TRUE: Enable custom preamble.
FALSE: Disable custom preamble.
|
FALSE
|
|
Testing Attributes
|
|
CTL_TEST_MODE_PIN_CHAR
|
Boolean
|
Reserved. Set to FALSE.
|
FALSE
|
|
TEST_MODE_PIN_CHAR
|
Boolean
|
Reserved. Set to FALSE.
|
FALSE
|