The user side interface of the UltraScale+ Devices Integrated 100G Ethernet IP core is a simple packet interface referred to as the LBUS. The LBUS interface implemented in the 100G Ethernet IP core is 512-bits segmented.
The LBUS consists of three separate interfaces:
•Transmitter (TX) interface
•Receiver (RX) interface
•Status/Control interface
The transmitter accepts packet-oriented data, packages the data in accordance with the IEEE 802.3 Specification, and sends that packaged data to the serial transceiver interface. The transmitter has control/configuration inputs to shape the data packaging to meet design-specific requirements.
The receiver accepts IEEE 802.3 data streams from the serial transceiver interface and provides packet-oriented data to the user side.
The status/control interface is used to set the characteristics of the interface and monitor its operation.
The 100G Ethernet IP core employs a segmented LBUS interface to prevent the loss of potential bandwidth that occurs at the end of a packet when the size of the packet is not a multiple of the LBUS width.
The segmented LBUS is a collection of narrower LBUSs, each 128 bits wide, with multiple transfers presented in parallel during the same clock cycle. Each segment has all the control signals associated with a complete 128-bit LBUS. The 512-bit segmented LBUS has four 128-bit segments with the signals for each segment shown in Table: Segmented LBUS Signals.
The transmit and receive signals are defined as follows:
•tx_datain0[127:0]: Transmit LBUS Data. This bus receives input data from the user logic. The value of the bus is captured in every cycle for which tx_enain is sampled as 1.
•tx_enain0: Transmit LBUS Enable. This signal is used to enable the TX LBUS Interface. All signals on the LBUS interface are sampled only in cycles during which tx_enain is sampled as 1.
•tx_sopin0: Transmit LBUS Start Of Packet. This signal is used to indicate the Start Of Packet (SOP) when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles during which tx_enain is sampled as 1.
•tx_eopin0: Transmit LBUS End Of Packet. This signal is used to indicate the End Of Packet (EOP) when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles during which tx_enain is sampled as 1.
•tx_errin0: Transmit LBUS Error. This signal is used to indicate a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles during which tx_enain and tx_eopin are sampled as 1.
•tx_mtyin0[3:0]: Transmit LBUS Empty. This bus is used to indicate how many bytes of the tx_datain bus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles that tx_enain and tx_eopin are sampled as 1.
When tx_eopin and tx_errin are sampled as 1, the value of tx_mtyin[2:0] is ignored as treated as if it is 000. The other bits of tx_mtyin are used as usual.
•rx_dataout0[127:0]: Receive LBUS Data. The value of the bus is only valid in cycles during which rx_enaout is sampled as 1.
•rx_enaout0: Receive LBUS Enable. This signal qualifies the other signal of the RX LBUS Interface. Signals of the RX LBUS Interface are only valid in cycles during which rx_enaout is sampled as 1.
•rx_sopout0: Receive LBUS Start-Of-Packet. This signal indicates the Start Of Packet (SOP) when it is sampled as 1 and is only valid in cycles during which rx_enaout is sampled as a 1.
•rx_eopout0: Receive LBUS End-Of-Packet. This signal indicates the End Of Packet (EOP) when it is sampled as 1 and is only valid in cycles during which rx_enaout is sampled as a 1.
•rx_errout0: Receive LBUS Error. This signal indicates that the current packet being received has an error when it is sampled as 1. This signal is only valid in cycles when both rx_enaout and rx_eopout are sampled as a 1. When this signal is 0, it indicates that there is no error in the packet being received.
•rx_mtyout0[3:0]: Receive LBUS Empty. This bus indicates how many bytes of the rx_dataout bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both rx_enaout and rx_eopout are sampled as 1.
When rx_errout and rx_enaout are sampled as 1, the value of rx_mtyout[2:0] is always 000. Other bits of rx_mtyout are as usual.
The transmitter accepts packet-oriented data. The transmitter has control/configuration inputs to shape the data packaging to meet design-specific requirements. The receiver accepts Ethernet bitstreams from the SerDes and provides packet-oriented data to the user side segmented LBUS.
IMPORTANT: In the following section, the term "asserting" is used to mean "assigning a value of 1," and the term "negating" is used to mean "assigning a value of 0."