Between the CAUI-10 and CAUI-4 modes, the PCS multiplexer blocks combine and distribute the PMD lanes from the SerDes to the internal PCS lane logic. This Figure illustrates the multiplexing and demultiplexing function contained in the RX and TX PCS multiplexer blocks for the SerDes interfaces which are 80 bits wide. The lower 32 bits are used in CAUI-10 mode.
The preceding pattern is repeated for the other three 80-bit SerDes interfaces.
Each 80-bit SerDes interface is actually composed of a 16-bit group and a 64-bit group. The mapping of these two groups onto the 80-bit interface is illustrated in This Figure and This Figure for RX and TX respectively.
Note: The connectivity between the 100G Ethernet IP RX SerDes data interface to the GTY transceiver RX datapath for CAUI-10 and CAUI-4/100GAUI-4 operation is taken care of in the 100G Ethernet IP core.
Note: The connectivity between the 100G Ethernet IP TX SerDes data interface to the GTY transceiver TX datapath for CAUI-10 and CAUI-4/100GAUI-4 operation is taken care of in the 100G Ethernet IP core.
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X-Ref Target - Figure 3-10 
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