The DisplayPort 1.4 RX Subsystem supports
Versal®
devices and uses a fabric 8B10B
decoder implementation instead of a Xilinx transceiver block 8B10B
decoder. For Versal devices,
this results in an additional clock in the subsystem. The following table provides clock
frequency values.
Clock | Formula | Value |
---|---|---|
rx_lnk_clk | Link Rate/16 |
|
rx_dec_clk | Link Rate/20 |
|
The subsystem supports block automation in IPI for Versal device designs and instantiates the transceiver bridge (PHY) IP
and Versal transceiver wizard IP as part of block
automation.
Note: The rx_lnk_clk and rx_dec_clk are generated from the
same clock source. For example, the rx_dec_clk can be generated from the MMCM by
taking the rx_lnk_clk as an input clock. For more information, see the Example Design chapter for the VCK190 pass-through
example design IPI.