Designing with the Core - 1.0 English

Audio Formatter LogiCORE IP Product Guide (PG330)
Document ID
PG330
Release Date
2020-07-08
Version
1.0 English

This section includes guidelines and additional information to facilitate designing with the core.

Memory Structure

The Audio Formatter writes or reads from memory, assuming a cyclic buffer with programmed number of periods. S2MM and MM2S are completely independent and the number of periods, period size, and buffer addresses can vary for both.

The core starts writing to the buffer start address as programmed, and comes back to the buffer start address after finishing all the periods. The buffer start address can be modified while DMA is still in operation, but the new address is sampled only after finishing all the transfers, which is the period size of data multiplied by the number of periods programmed (i.e., size of buffer).

In Interleaved mode, the data from all the channels is ordered from 0 to Max number of channels, and placed in memory at consecutive address locations. Whereas in Non-Interleaved mode, all the data from each channel is placed together in order in a period.

Figure 1. Buffer
Table 1. Alignment of Data at Consecutive Addresses. The following figure shows the alignment of data at consecutive addresses in a period where L1, L2, L3, and L4 are channel 0 data, and R1, R2, R3, R4 are channel 1 data.
  Address Non-Interleaved 32-bit Interleaved Mode 32-bit Non-Interleaved 16-bit Interleaved 16-bit
Period N PSA 1 = BSA 2 + N(PS 3 ) L1 L1 L2 L1 R1 L1
PSA + ‘h4 L2 R1 L4 L3 R2 L2
PSA + ‘h8 L3 L2 L6 L5 R3 L3
PSA + ‘hC L4 R2 L8 L7 R4 L4

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PSA + CO 4 R1 Lx R2 R1 Ra La
PSA + CO + ‘h4 R2 RX R4 R3 Rb Lb
PSA + CO + ‘h8 R3 Ly R6 R5 Rc Lc
PSA + CO + ‘hC R4 Ry R8 R7 Rd Ld

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  1. Period Start Address (PSA)
  2. Buffer Start Address (BSA)
  3. Period Size (PS)
  4. Channel Offset (CO)
Note:

The period size constraints mentioned in the register description must be strictly followed. The functionality is not guaranteed otherwise.

S2MM Operations

The Audio Formatter core collects audio data from 2,4,6, or 8 audio channels as programmed through register and writes the data to memory in a packaged format. When the input data is AES, the core has an AES decoder block to get the channel status information of the audio stream. S2MM supports any order of data input channels and append zeroes for missing samples. S2MM also has a timeout logic to know if the source stops sending data.

When the core is enabled for S2MM, it readily accepts the audio input stream even before the DMA is enabled through registers. All this data is used only for channel status calculation and is not saved to write to memory when DMA is enabled.

AES Decoder

AES Decoder block is included in the core when the write is enabled and the input audio stream is selected as AES. The AES Decode logic is reset only with the hard reset to the system and the soft reset to S2MM programmed through register.

This module keeps accumulating the Channel status bit on the AES input and generates a flag when all the 192 bits are updated. The channel status thus inferred and the update indication flag are register readable. The flag is cleared once the register is read and is set when the channel status is updated or differs from the previous value.

Timeout Logic

The S2MM core gives an error indication when there is no valid audio input for a long time on the audio channels. A counter runs on the S2MM AXI4 clock when the S2MM DMA is enabled. Counter increments when input TVALID is low and refreshes when TVALID is high. When the counter reaches the programmed value in register, it generated timeout error which can be read through register. It can also generate an interrupt when configured.

Timeout error is cleared only through hard or soft reset.

Note: The timeout count must be updated before starting the DMA. The change in the count value after starting the DMA will not be considered.
Missing Samples

In this core, we assume that the input audio samples of different channels can come in any order but before the second set of samples from any of the channels arrives.

For example, in a 2-channel system, if the incoming samples are in the following order:

1,2,2,1,1,1,2

{1,2}, {2,1}, {1 ?}

Here, the expectation is a 2 after 1 to complete the third set. However, another sample from channel 1 arrived that indicates a sample from channel 2 is missing. Hence, 0 is added as data for second channel for third set. The final data would be:

{1,2}, {2,1} (will be re-ordered), {1,0}, {1,2}

{1,2}, {1,2}, {1,0}, {1,2}

Note: The core has a buffer logic inside which saves the channel data up to 8 samples. So the core flushes 8 samples of data per channel onto AXI4 Memory Map interface at once when all the 8 samples per channel are received or when the ninth sample of any of the channel is received in case of missing samples.

MM2S Operations

The core reads the data from the memory, and based on the memory organization programmed, the core rearranges the read data into multiple channels and sends it as an output AXI4-Stream at a sampling rate.

The core has a master clock “aud_mclk” whose frequency is known. Based on the required sampling rate, the Fs multiplier value is programmed through the register.

Sampling frequency = Frequency of aud_mclk/Fs multiplier Value

When the data in memory is selected as PCM and output data format is AES, the core adds AES information to the available PCM data. The channel status information is added as programmed through registers before starting DMA. The first data out is the start of block. The data on MM2S is sent out in order of channels from 0 to N-1.

The data on MM2S is sent out in order of channels from 0 to N-1.

Programming Sequence for S2MM

  1. Program bit run/stop in register 0x10 after programming all other S2MM related registers.
  2. Programming 0x1C, 0x20, 0x24, and 0x44 is required and to be done only when bit 0 of 0x10 is 0.
    1. Program 0x1C for a valid period size and no. of periods in a buffer. If constraints on period size are not met, functionality of the core is not guaranteed.
    2. Programming 0x24 register can be skipped if Address width is 32 bits.
    3. Program channel offset in 0x44 register with a value = period size / no. of valid channels. This register can be skipped when C_PACKAGING_MODE_S2MM = 0 (Interleaved mode).
  3. Program register 0x18, if timeout error interrupt is required.
  4. Program 0x10 in the end with the no. of valid channels and PCM data width. Enable the respective interrupts required.
  5. Program 0x10 to start DMA making bit 0 to 1.
    • This can be clubbed with step IV.

Programming Sequence for MM2S

  1. Program bit run/stop in register 0x110 after programming all other MM2S related registers.
  2. Programming 0x118, 0x11C, 0x120, 0x124, and 0x144 is required and to be done only when bit 0 of 0x110 is 0.
    1. Program 0x118 with “fs_multiplier_value” to generate the output stream samples at this rate.
    2. Program 0x11C for a valid period size and no. of periods in a buffer. If constraints on period size are not met, functionality of the core is not guaranteed.
    3. Programming 0x124 register can be skipped if Address width is 32 bits.
    4. Program channel offset in 0x144 register with a value = period size / no. of valid channels. This register can be skipped when C_PACKAGING_MODE_MM2S = 0 (Interleaved mode).
  3. Program registers 0x12C to 0x140 with AES channel status when C_MM2S_DATAFORMAT = 3. In other data-formats these registers can be ignored.
  4. Program 0x110 in the end with the no. of valid channels and PCM data width. Enable the respective interrupts required.
  5. Program 0x110 to start DMA making bit 0 to 1.
    • This can be clubbed with step 4.
Note: Do not modify any of the above-mentioned registers when Run/Stop bit is 1. The core behavior is not guaranteed otherwise.