Click FIFO Data in any RF-ADC or RF-DAC channel to see the clock relationship of the converter tile, PL interface, and related MMCM configuration.
Figure 1. FIFO Data
Note: The clock scheme is tile
based, which means all converter channels in one tile share the same clock
scheme.
Note: In an MTS enabled
bitstream, all RF-ADC tiles share one MMCM module in
ADC Tile-0. All RF-DAC tiles share one MMCM module in
DAC Tile-0. Values in the FIFO Data page of other tiles are invalid.
The following values are configurable in the FIFO Data page.
- FabCLKDiv
- In a non-MTS bitstream, the converter sampling clock (Fs, also called T1) is divided by 8 or 4 and then divided by FabCLKDiv. The output goes to the MMCM module as an input reference.
- M, D, and ClkDiv
- In the MMCM module, the MMCM generates a read or write clock for
the FIFO on the PL side, which is shown as F(PL) in the FIFO Data page. The
following formula can be used to calculate the PL FIFO clock.
F(PL)=Fin*M/D/ClkDiv
Note: The VCO in the MMCM has a
limited frequency range requirement. See
Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching
Characteristics (DS926) for the VCO frequency range for different devices.
The proper values for the FIFO related clock configurations are set automatically based on user configuration in the clock distribution page and converter configurations. Generally, these values do not need to be changed.