NOC_NMU128 - 2021.2 English

Versal Architecture AI Core Series Libraries Guide (UG1353)

Document ID
UG1353
Release Date
2021-10-22
Version
2021.2 English

Primitive: NoC Master Unit

  • PRIMITIVE_GROUP: ADVANCED
  • PRIMITIVE_SUBGROUP: BUFFER

Introduction

The NOC_NMU128 is a NoC Component in Versal devices. This element is not intended to be instantiated, used, or modified outside of Xilinx-generated IP.

Design Entry Method

Instantiation No
Inference No
IP and IP Integrator Catalog Recommended

Related Information

  • Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)