Typical Operation Type in CNN | Parameters | DPUCZDX8G_ISA1_B4096 (ZCU102, ZCU104) | DPUCAHX8L_ISA0 (U50, U50LV, U280) | DPUCVDX8G_ISA3_C32B3 (VCK190) | DPUCAHX8H_ISA2_DWC 1 (U50, U55C, U50LV, U280) | DPUCADF8H_ISA0 (U200, U250) | DPUCVDX8H_ISA1_F2W4_4PE 2 (VCK5000) |
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Intrinsic Parameter | channel_parallel: 16 bank_depth: 2048 bank_num: 8 |
channel_parallel: 32 bank_depth: 4096 |
channel_parallel: 16 bank_depth: 8192 bank_num: 8 |
channel_parallel: 16 bank_depth: 2048 |
channel_parallel: 16 bank_depth: 8192 |
channel_parallel: 64 bank_depth: 2048 |
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conv2d | Kernel size | w, h: [1, 16] | w, h: [1, 16] | w, h: [1, 16] w * h * ceil(input_channel/2048) <= 64 |
w, h: [1, 16] | w, h: [1, 16] | w, h: [1, 16] |
Strides | w, h: [1, 8] | w, h: [1, 4] | w, h: [1, 8] | w, h: [1, 4] | w, h: [1, 8] | w, h: [1, 4] | |
Dilation | dilation * input_channel <= 256 * channel_parallel | ||||||
Paddings | pad_left, pad_right: [0, (kernel_w - 1) * dilation_w] | ||||||
pad_top, pad_bottom: [0, (kernel_h - 1) * dilation_h] | |||||||
In Size | kernel_w * kernel_h * ceil(input_channel / channel_parallel) <= bank_depth | ||||||
Out Size | output_channel <= 256 * channel_parallel | ||||||
Activation | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | ReLU, ReLU6 | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | ReLU, LeakyReLU, ReLU6 | ReLU, LeakyReLU | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | |
Group* (Caffe) | group==1 | ||||||
depthwise-conv2d | Kernel size | w, h: [1, 256] | w, h: [3] | w, h: [1, 256] | w, h: {1, 2, 3, 5, 7} | Not supported | w, h: [1, 8] |
Strides | w, h: [1, 256] | w, h: [1, 2] | w, h: [1, 256] | w, h: [1, 4] | w, h : [1, 4] | ||
dilation | dilation * input_channel <= 256 * channel_parallel | dilation * input_channel <= 256 * channel_parallel | |||||
Paddings | pad_left, pad_right: [0, min((kernel_w - 1), 15) * dilation_w] | pad_left, pad_right: [0, (kernel_w - 1) * dilation_w] | pad_left, pad_right: [0, min((kernel_w-1), 15) * dilation_w] | pad_left, pad_right: [0, (kernel_w - 1) * dilation_w] | pad_left, pad_right: [0, (kernel_w - 1) * dilation_w] | ||
pad_top, pad_bottom: [0, min((kernel_h - 1), 15) * dilation_h] | pad_top, pad_bottom: [0, (kernel_h - 1) * dilation_h] | pad_top, pad_bottom: [0, min((kernel_h-1), 15) * dilation_h] | pad_top, pad_bottom: [0, (kernel_h - 1) * dilation_h] | pad_top, pad_bottom: [0, (kernel_h - 1) * dilation_h] | |||
In Size | kernel_w * kernel_h * ceil(input_channel / channel_parallel) <= bank_depth | kernel_w * kernel_h * ceil(input_channel / channel_parallel) <= bank_depth | |||||
Out Size | output_channel <= 256 * channel_parallel | output_channel <= 256 * channel_parallel | |||||
Activation | ReLU, ReLU6, LeakyReLU, Hard-Swish, Hard-Sigmoid | ReLU, ReLU6 | ReLU, ReLU6, LeakyReLU, Hard-Swish, Hard-Sigmoid | ReLU, ReLU6 | ReLU, ReLU6 | ||
Group* (Caffe) | group==input_channel | group==input_channel | |||||
transposed-conv2d | Kernel size | kernel_w/stride_w, kernel_h/stride_h: [1, 16] | |||||
Strides | |||||||
Paddings | pad_left, pad_right: [0, kernel_w-1] | ||||||
pad_top, pad_bottom: [0, kernel_h-1] | |||||||
Out Size | output_channel <= 256 * channel_parallel | ||||||
Activation | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | ReLU, ReLU6 | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | ReLU, LeakyReLU, ReLU6 | ReLU, LeakyReLU | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | |
depthwise-transposed-conv2d | Kernel size | kernel_w/stride_w, kernel_h/stride_h: [1, 256] | kernel_w/stride_w, kernel_h/stride_h: [3] | kernel_w/stride_w, kernel_h/stride_h: [1, 256] | kernel_w/stride_w, kernel_h/stride_h: {1,2, 3, 5, 7} | Not supported | kernel_w/stride_w, kernel_h/stride_h: [1, 8] |
Strides | |||||||
Paddings | pad_left, pad_right: [0, min((kernel_w-1), 15)] | pad_left, pad_right: [1, kernel_w-1] | pad_left, pad_right: [0, min((kernel_w-1),15)] | pad_left, pad_right: [1, kernel_w-1] | pad_left, pad_right: [1, kernel_w-1] | ||
pad_top, pad_bottom: [0, min((kernel_h-1), 15)] | pad_top, pad_bottom: [1, kernel_h-1] | pad_top, pad_bottom: [0, min((kernel_h-1), 15)] | pad_top, pad_bottom: [1, kernel_h-1] | pad_top, pad_bottom: [1, kernel_h-1] | |||
Out Size | output_channel <= 256 * channel_parallel | output_channel <= 256 * channel_parallel | |||||
Activation | ReLU, ReLU6, LeakyReLU, Hard-Swish, Hard-Sigmoid | ReLU, ReLU6 | ReLU, ReLU6, LeakyReLU, Hard-Swish, Hard-Sigmoid | ReLU, ReLU6 | ReLU, ReLU6 | ||
max-pooling | Kernel size | w, h:
[1,
256] ceil(h/bank_num) * w <= bank_depth |
w, h: {2, 3, 5, 7, 8} | w, h: [1,
256] ceil(h/bank_num) * w <= bank_depth |
w, h: [1, 8] | w, h: [1, 16] | w, h: [1, 128] |
Strides | w, h: [1, 256] | w, h: [1, 8] | w, h: [1, 256] | w, h: [1, 8] | w, h: [1, 8] | w, h: [1, 128] | |
Paddings | pad_left, pad_right: [0, min((kernel_w-1), 15)] | pad_left, pad_right: [1, kernel_w-1] | pad_left, pad_right: [0, min((kernel_w-1), 15)] | pad_left, pad_right: [1, kernel_w-1] | |||
pad_top, pad_bottom: [0, min((kernel_h-1), 15)] | pad_top, pad_bottom: [1, kernel_h-1] | pad_top, pad_bottom: [0, min((kernel_h-1), 15)] | pad_top, pad_bottom: [1, kernel_h-1] | ||||
Activation | ReLU, ReLU6 | not supported | ReLU, ReLU6 | not supported | ReLU | not supported | |
average-pooling | Kernel size | w, h: [1, 256] ceil(h/bank_num) * w <= bank_depth |
w, h: {2, 3, 5, 7, 8} w==h |
w, h: [1, 256] ceil(h/bank_num) * w <= bank_depth |
w, h: [1, 8] w==h |
w, h: [1, 16] | w, h: [1, 128] w==h |
Strides | w, h: [1, 256] | w, h: [1, 8] | w, h: [1, 256] | w, h: [1, 8] | w, h: [1, 8] | w, h: [1, 128] | |
Paddings | pad_left, pad_right: [0, min((kernel_w-1), 15)] | pad_left, pad_right: [1, kernel_w-1] | pad_left, pad_right: [0, min((kernel_w-1), 15)] | pad_left, pad_right: [1, kernel_w-1] | |||
pad_top, pad_bottom: [0, min((kernel_h-1), 15)] | pad_top, pad_bottom: [1, kernel_h-1] | pad_top, pad_bottom: [0, min((kernel_h-1), 15)] | pad_top, pad_bottom: [1, kernel_h-1] | ||||
Activation | ReLU, ReLU6 | not supported | ReLU, ReLU6 | not supported | ReLU | not supported | |
eltwise | type | sum, prod | sum | sum, prod | sum | sum | sum, prod |
Input Channel | input_channel <= 256 * channel_parallel | ||||||
Activation | ReLU | ReLU | ReLU | ReLU | ReLU | ReLU, Hard-Sigmoid | |
concat | Network-specific limitation, which relates to the size of feature maps, quantization results and compiler optimizations. | ||||||
reorg | Strides | reverse==false :
stride ^ 2 * input_channel <= 256 * channel_parallel reverse==true : input_channel <= 256 * channel_parallel |
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pad | In Size | input_channel <= 256 * channel_parallel | |||||
Mode | "SYMMETRIC" ("CONSTANT" pad(value=0) would be fused into adjacent operators during compiler optimization process) | "SYMMETRIC", "CONSTANT" (all padding value are identical) | |||||
global pooling | Global pooling will be processed as general pooling with kernel size equal to input tensor size. | ||||||
InnerProduct, Fully Connected, Matmul | These ops will be transformed into conv2d op | ||||||
resize | scale | NEAREST:
ceil(scale/bank_num) * scale * ceil(input_channel/channel_parallel)
<= bank_depth BILINEAR: only for 4-D feature maps. This would be transformed into pad and depthwise-transposed-conv2d. TRILINEAR: only for 5-D feature maps. This would be transformed into pad and transposed-conv3d. |
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mode | NEAREST, BILINEAR | NEAREST, BILINEAR | NEAREST, BILINEAR, TRILINEAR | NEAREST, BILINEAR | NEAREST, BILINEAR | NEAREST, BILINEAR | |
conv3d | kernel size | Not supported | Not supported | w,
h, d: [1, 16] w * h * ceil(ceil(input_channel/16) * 16 * d / 512) <= 64 |
Not supported | Not supported | Not supported |
strides | w, h, d: [1, 8] | ||||||
paddings | pad_left,
pad_right: [0, kernel_w-1] pad_top, pad_bottom: [0, kernel_h-1] pad_front, pad_back: [0, kernel_d-1] |
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In size | kernel_w * kernel_h * kernel_d * ceil(input_channel/channel_parallel) <= bank_depth | ||||||
Out size | output_channel <= 256 * channel_parallel | ||||||
Activation | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | ||||||
depthwise-conv3d | kernel size | Not supported | Not supported | w,
h: [1, 256] d: [1, 16] |
Not supported | Not supported | Not supported |
strides | w,
h: [1, 256] d=1 |
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paddings | pad_left,
pad_right: [0, min((kernel_w-1), 15)] pad_top, pad_bottom: [0, min((kernel_h-1), 15)] pad_front, pad_back: [0, min((kernel_d-1), 15)] |
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In size | kernel_w * kernel_h * kernel_d * ceil(input_channel/channel_parallel) <= bank_depth | ||||||
Out size | output_channel <= 256 * channel_parallel | ||||||
Activation | ReLU, ReLU6 | ||||||
transposed-conv3d | kernel size | Not supported | Not supported | kernel_w/stride_w, kernel_h/stride_h, kernel_d/stride_d: [1, 16] | Not supported | Not supported | Not supported |
strides | |||||||
paddings | pad_left,
pad_right: [0, kernel_w-1] pad_top, pad_bottom: [0, kernel_h-1] pad_front, pad_back: [0, kernel_d-1] |
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Out size | output_channel <= 256 * channel_parallel | ||||||
Activation | ReLU, LeakyReLU, ReLU6, Hard-Swish, Hard-Sigmoid | ||||||
depthwise-transposed-conv3d | kernel size | Not supported | Not supported | kernel_w/stride_w, kernel_h/stride_h, kernel_d/stride_d: [1, 16] | Not supported | Not supported | Not supported |
strides | |||||||
paddings | pad_left, pad_right: [0, min((kernel_w-1), 15)] pad_top, pad_bottom: [0, min((kernel_h-1), 15)] pad_front, pad_back: [0, min((kernel_d-1), 15)] |
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Out size | output_channel <= 256 * channel_parallel | ||||||
Activation | ReLU, ReLU6 | ||||||
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