Register Space (Legacy and Enhanced Non-XIP Mode) - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
PG153
Release Date
2022-04-26
Version
3.2 English

Note:   The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.

Table: Core Registers in Legacy and Enhanced Mode shows the set of registers applicable whether or not Enable Performance Mode is selected and Enable XIP Mode is not selected. Some AXI Quad SPI core registers should be accessed individually. These registers are configurable and accessible through either the AXI4-Lite interface or the AXI4 interface (enhanced mode). All registers are accessed as 32-bit. If non-existent registers are accessed, they return an OKAY response. The reading of these registers returns 0, and write does not have any affect.

Table 2-3:      Core Registers in Legacy and Enhanced Mode

Address Space Offset

Register Name

Access Type

Default Value (hex)

Description

Core Grouping

40h

SRR

Write

N/A

Software reset register

60h

SPICR

R/W

0x180

SPI control register

64h

SPISR

Read

0x0a5

SPI status register

68h

SPI DTR

Write

0x0

SPI data transmit register. A single register or a FIFO

6Ch

SPI DRR

Read

N/A(1)

SPI data receive register. A single register or a FIFO

70h

SPISSR

R/W

No slave is selected
0xFFFF

SPI Slave select register

74h

SPI Transmit FIFO Occupancy Register(2)

Read

0x0

Transmit FIFO occupancy register

78h

SPI Receive FIFO Occupancy Register(2)

Read

0x0

Receive FIFO occupancy register

Interrupt Control Grouping

1Ch

DGIER

R/W

0x0

Device global interrupt enable register

20h

IPISR

R/TOW(3)

0x0

IP interrupt status register

28h

IPIER

R/W

0x0

IP interrupt enable register

Notes:

1.The power-on reset data in the SPI DRR is unknown or all zeros. This register should not be considered for power-on reset conditions.

2.Exists only when FIFO Depth is set to 16 or 256.

3.TOW = Toggle on write. Writing a 1 to a bit position within the register causes the corresponding bit position in the register to toggle.