The Interrupt Enable Register (IPIER) register allows the system interrupt output to be active. This interrupt is generated if an active bit in the IPISR register corresponds to an enabled bit in the IPIER register. The IPIER register has an enable bit for each defined bit of the IPISR as shown in This Figure and described in Table: IP Interrupt Enable Register Description (Core Base Address + 0x28). All bits are cleared on reset.
Figure 2-11: IP Interrupt Enable Register (Core Base Address + 0x28)
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X-Ref Target - Figure 2-11
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Table 2-14: IP Interrupt Enable Register Description (Core Base Address + 0x28)
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Bits
|
Name
|
Core Access
|
Reset Value
|
Description
|
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31:14
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Reserved
|
N/A
|
N/A
|
Reserved
|
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13
|
Command Error
|
R/W
|
0
|
Command error.
0 = Disabled.
1 = Enabled.
This bit is applicable only when the core is configured in dual or quad SPI mode.
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12
|
Loopback Error
|
R/W
|
0
|
Loopback error.
0 = Disabled.
1 = Enabled.
This bit is applicable only when the core is configured in dual or quad SPI mode.
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11
|
MSB Error
|
R/W
|
0
|
MSB error.
0 = Disabled.
1 = Enabled.
This bit is applicable only when the core is configured in dual or quad SPI mode.
|
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10
|
Slave Mode Error
|
R/W
|
0
|
I/O mode instruction error.
0 = Disabled.
1 = Enabled.
This bit is applicable only when the core is configured in dual or quad SPI mode.
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9
|
CPOL_CPHA Error
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R/W
|
0
|
CPOL_CPHA error.
0 = Disabled.
1 = Enabled.
This bit is applicable only when the core is configured in dual or quad SPI mode.
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8
|
DRR_Not_
Empty
|
R/W
|
0
|
DRR_Not_Empty.
0 = Disabled.
1 = Enabled.
Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.
If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.
This bit has no significance in dual or quad mode.
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7
|
Slave_Select_
Mode
|
R/W
|
0
|
Slave_Select_Mode.
0 = Disabled.
1 = Enabled.
This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel. In master mode, setting this bit has no effect.
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6
|
TX FIFO Half Empty
|
R/W
|
0
|
Transmit FIFO half empty.
0 = Disabled.
1 = Enabled.
Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.
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5
|
DRR Overrun
|
R/W
|
0
|
Receive FIFO overrun.
0 = Disabled.
1 = Enabled.
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4
|
DRR Full
|
R/W
|
0
|
Data receive register/FIFO full.
0 = Disabled.
1 = Enabled.
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3
|
DTR Underrun
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R/W
|
0
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Data transmit FIFO underrun.
0 = Disabled.
1 = Enabled.
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2
|
DTR Empty
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R/W
|
0
|
Data transmit register/FIFO empty.
0 = Disabled.
1 = Enabled.
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|
1
|
Slave MODF
|
R/W
|
0
|
Slave mode-fault error flag.
0 = Disabled.
1 = Enabled.
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0
|
MODF
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R/W
|
0
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Mode-fault error flag.
0 = Disabled.
1 = Enabled.
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