The SPI Receive FIFO Occupancy Register (RX_FIFO_OCY) is present only if the AXI Quad SPI core is configured with FIFOs (FIFO Depth = 16 or 256). If the register is present and if the receive FIFO is not empty, the register contains a four-bit, right-justified value that is one less than the number of elements in the FIFO (occupancy minus one).
This register is read-only. A write to it (or of a read when the FIFO is empty) does not affect the register contents. The only reliable way to determine that the receive FIFO is empty/full is by reading the Rx_Empty/Rx_Full status bit in the SPI status register.
The receive FIFO occupancy register is shown in This Figure, while the specifics of the data format are described in Table: SPI Receive FIFO Occupancy Register Description (Core Base Address + 0x78).
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