The following table shows the relationship between the fields in the Vivado® IDE and the User Parameters (which can be viewed in the Tcl Console).
Vivado IDE Parameter/Value 1 | User Parameter/Value 1 | Default Value |
---|---|---|
Number of Optimized AXI4 Ports | C_NUM_OPTIMIZED_PORTS | 1 |
Number of Generic AXI4 Ports | C_NUM_GENERIC_PORTS | 0 |
Enable Slave Coherency | C_ENABLE_SLAVE_COHERENCY | 0 |
None | 0 | |
ACE Coherency Protocol | 1 | |
Enable Master Coherency | C_ENABLE_MASTER_COHERENCY | 0 |
None | 0 | |
ACE Coherency Protocol | 1 | |
CCIX Coherency Protocol | 2 | |
CHI Coherency Protocol | 3 | |
Enable Integrity | C_ENABLE_INTEGRITY | 0 |
Enable Exclusive Accesses | C_ENABLE_EXCLUSIVE | 0 |
N-Way Set Associative | C_NUM_WAYS | 2 |
Line Length | C_CACHE_LINE_LENGTH | 16 |
Size | C_CACHE_SIZE | 32k |
32k | 32768 | |
64k | 65536 | |
128k | 131072 | |
256k | 262144 | |
512k | 524288 | |
1M | 1048576 | |
2M | 2097152 | |
4M | 4194304 | |
Enable Exclusive Access | C_ENABLE_EXCLUSIVE | 0 |
Enable Non-Secure Access | C_ENABLE_NON_SECURE | 0 |
Enable AXI Error Handling | C_ENABLE_ERROR_HANDLING | 0 |
Tag RAM Type | C_CACHE_TAG_MEMORY_TYPE | 0 |
Automatic | 0 | |
LUTRAM | 1 | |
BRAM | 2 | |
URAM | 3 | |
Data RAM Type | C_CACHE_DATA_MEMORY_TYPE | 0 |
Automatic | 0 | |
BRAM | 2 | |
URAM | 3 | |
LRU RAM Type | C_CACHE_LRU_MEMORY_TYPE | 0 |
Automatic | 0 | |
LUTRAM | 1 | |
BRAM | 2 | |
URAM | 3 | |
M0_AXI Address Width | C_M0_AXI_ADDR_WIDTH | 32 |
M0_AXI Data Width | C_M0_AXI_DATA_WIDTH | 32 |
M0_AXI Thread ID Width | C_M0_AXI_THREAD_ID_WIDTH | 1 |
CXS0 Flit Data Width | C_CXS0_FLIT_DATA_WIDTH | 256 |
CXS0 Packet Header | C_CCIX0_PKT_HEADER | 0 |
Compatible | 0 | |
Optimized | 1 | |
CXS0 No Message Packing | C_CCIX0_NO_MSG_PACK | 1 |
Sx_AXI 2 | C_Sx_AXI_DATA_WIDTH 2 | 32 |
Sx_AXI_GEN 2 | C_Sx_AXI_GEN_DATA_WIDTH 2 | 32 |
M0_CHI Data Width | C_M0_CHI_DATA_WIDTH | 512 |
Enable AXI Control Interface | C_ENABLE_CTRL | 0 |
Select Statistics Groups | C_ENABLE_STATISTICS | 0 |
Enable Version Registers | C_ENABLE_VERSION_REGISTER | None |
None | 0 | |
Basic | 1 | |
Full | 2 | |
Enable Interrupt Output | C_ENABLE_INTERRUPT | 0 |
Support Downstream Snoop Filter | C_SUPPORT_SNOOP_FILTER | 0 |
Keep After ReadOnce | C_SNOOP_KEEP_READ_ONCE | 1 |
Keep After ReadShared | C_SNOOP_KEEP_READ_SHARED | 0 |
Keep After ReadClean | C_SNOOP_KEEP_READ_CLEAN | 0 |
Keep After ReadNotSharedDirty | C_SNOOP_KEEP_READ_NSD | 0 |
Keep After CleanShared | C_SNOOP_KEEP_CLEAN_SHARED | 0 |
Pass Dirty After ReadOnce | C_SNOOP_PASS_READ_ONCE | 0 |
Pass Dirty After ReadShared | C_SNOOP_PASS_READ_SHARED | 0 |
Pass Dirty After ReadClean | C_SNOOP_PASS_READ_CLEAN | 0 |
Pass Dirty After ReadNotSharedDirty | C_SNOOP_PASS_READ_NSD | 0 |
Default Sharability Domain | C_DEFAULT_DOMAIN | 0 |
Inner | 0 | |
Outer | 1 | |
Keep After SnpToAny | C_SNOOP_KEEP_READ_ONCE | 1 |
Keep After SnpToS | C_SNOOP_KEEP_READ_SHARED | 0 |
Keep After SnpToC | C_SNOOP_KEEP_READ_CLEAN | 0 |
Keep After SnpToSC | C_SNOOP_KEEP_SNPTOSC | 0 |
Pass Dirty After SnpToAny | C_SNOOP_PASS_READ_ONCE | 0 |
Pass Dirty After SnpToS | C_SNOOP_PASS_READ_SHARED | 0 |
SnpOnce_Keep_Line | C_SNOOP_KEEP_READ_ONCE | 1 |
SnpClean_Keep_Line | C_SNOOP_KEEP_READ_CLEAN | 0 |
SnpShared_Keep_Line | C_SNOOP_KEEP_READ_SHARED | 0 |
SnpNotSharedDirty_Keep_Line | C_SNOOP_KEEP_READ_NSD | 0 |
SnpCleanShared_Keep_Line | C_SNOOP_KEEP_CLEAN_SHARED | 0 |
SnpOnce_Pass_Dirty | C_SNOOP_PASS_READ_ONCE | 0 |
SnpClean_Pass_Dirty | C_SNOOP_PASS_READ_CLEAN | 0 |
SnpShared_Pass_Dirty | C_SNOOP_PASS_READ_SHARED | 0 |
SnpNotSharedDirty_Pass_Dirty | C_SNOOP_PASS_READ_NSD | 0 |
Number of SAM Entries | C_NUM_SAM_ENTRIES | 1 |
Valid | C_SAMx_VALID 3 | 0 |
ID | C_SAMx_ID 3 | 0 |
Base Address | C_:SAMx_BASEADDR 3 | 0xFFFFFFFFFFFFFFFF |
High Address | C_SAMx_HIGHADDR 3 | 0x0000000000000000 |
Enable Address Translation | C_ENABLE_ADDRESS_TRANSLATION | 0 |
None | 0 | |
ATS | 1 | |
ATS0 Data Width | C_ATS0_DATA_WIDTH | 256 |
ATS0 CQ and CC Alignment Mode | C_ATS0_CQ_CC_ALIGNMENT_MODE | 0 |
DWORD Aligned | 0 | |
Address Aligned | 1 | |
ATS0 RQ and RC Alignment Mode | C_ATS0_RQ_RC_ALIGNMENT_MODE | 0 |
DWORD Aligned | 0 | |
Address Aligned | 1 | |
ATS0 CQ and CC Frame Straddle 5 | C_ATS0_CQ_CC_STRADDLE | 0 |
ATS0 RC Frame Straddle 4 | C_ATS0_RQ_RC_STRADDLE | 1 |
ATS0 RQ and RC Frame Straddle 4 | C_ATS0_RQ_RC_STRADDLE | 1 |
ATS0 PASID Mode | C_ATS0_PASID_MODE | 0 |
ATS0 Parity | C_ATS0_PARITY | 0 |
DISABLE | 0 | |
GENERATE | 1 | |
GENERATE CHECK | 2 | |
ATS0 PRI Timeout Limit (ms) | C_ATS0_PRI_TIMEOUT_LIMIT | 10 |
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