| Parameter Name | Feature/Description |
Allowable Values |
Default Value |
VHDL Type |
|---|---|---|---|---|
| C_FAMILY 4 | FPGA Architecture | Supported architectures | virtex7 | string |
| C_INSTANCE 4 | Instance Name | Any instance name | system_cache | string |
| C_FREQ 4 | System Cache clock frequency | Any valid frequency for the device | 0 | natural |
| C_BASEADDR 4 | Cacheable area base address | 0xFFFF FFFF FFFF FFFF | std_logic_vector | |
| C_HIGHADDR 4 |
Cacheable area high address. Minimum size is 32KB |
0x0000 0000 0000 0000 | std_logic_vector | |
| C_ENABLE_COHERENCY 1 |
Enable implementation of cache coherent optimized ports |
0, 1, 2 | 0 | natural |
| C_ENABLE_SLAVE_COHERENCY | Enable implementation of cache coherent slave ports | 0, 1 | 0 | natural |
| C_ENABLE_MASTER_COHERENCY | Enable implementation of cache coherent master ports | 0, 1, 2, 3 | 0 | natural |
| C_ENABLE_ACE_PROTOCOL 1 | Enable ACE protocol | 0, 1 | 0 | natural |
| C_ENABLE_CCIX_PROTOCOL 1 | Enable CCIX protocol | 0, 1 | 0 | natural |
| C_ENABLE_CHI_PROTOCOL 1 | Enable CHI protocol | 0, 1 | 0 | natural |
| C_ENABLE_INTEGRITY | Enable Integrity | 0, 1 | 0 | natural |
| C_ENABLE_EXCLUSIVE |
Enable implementation of exclusive monitor for non-coherent implementation |
0, 1 | 0 | natural |
| C_ENABLE_NON_SECURE |
Enable distinction between Secure and Non-Secure transactions |
0,1 | 0 | natural |
| C_ENABLE_ERROR_HANDLING |
Make RRESP with any error value drop an allocation attempt |
0,1 | 0 | natural |
| C_ENABLE_CTRL |
Enable implementation of Statistics and Control function |
0, 1 | 0 | natural |
| C_ENABLE_STATISTICS |
Bit mask for which statistics groups implemented when Control Interface is enabled: xxxx_xxx1 - Optimized Ports xxxx_xx1x - Generic Port xxxx_x1xx - Arbiter xxxx_1xxx - Access xxx1_xxxx - Lookup xx1x_xxxx - Update x1xx_xxxx - Backend 1xxx_xxxx - ATC |
0-255 | 255 | natural |
| C_ENABLE_VERSION_REGISTER |
Level of Version Register to include: 0 - None 1 - Basic 2 - Full |
0, 1, 2 | 0 | natural |
| C_ENABLE_INTERRUPT | Enable control interface interrupt output | 0, 1 | 0 | natural |
| C_ENABLE_ADDRESS_TRANSLATION | Enable address translation cache: 0 - None 1 - ATS |
0, 1 | 0 | natural |
| C_NUM_OPTIMIZED_PORTS |
Number of ports optimized for MicroBlaze processor cache connection |
0-16 2 | 1 | natural |
| C_NUM_GENERIC_PORTS |
Number of ports supporting full AXI4 |
0-16 3 | 0 | natural |
| C_NUM_MASTER_PORTS | Number of master ports | 0, 1 | 1 | natural |
| C_NUM_WAYS | Cache associativity | 2, 4 | 2 | natural |
| C_NUM_SLAVE_TRANSACTIONS 4 | Slave transactions in-flight per port | 16, 32, 64, 128, 256 | 16 | natural |
| C:_NUM_MASTER_TRANSACTIONS 4 | Master transactions in-flight | 16, 32, 64, 128, 256 | 16 | natural |
| C_NUM_SNOOP_TRANSACTIONS 4 | Snoop transactions in-flight | 16, 32, 64, 128, 256 | 16 | natural |
| C_NUM_OOO_CHANNELS 4 | Number of out-of-order channels | 0 - 16 |
0 (AXI, ACE) 1 (CCIX, CHI) |
natural |
| C_CACHE_DATA_WIDTH |
Cache data width used internally. Automatically calculated to match AXI4 master interface |
32, 64, 128, 256, 512 |
32 | natural |
| C_CACHE_LINE_LENGTH |
Cache line length. Constant value for ACE, CCIX. and CHI |
16, 32, 64, 128, 256, 512, 1024 | 16 | natural |
| C_CACHE_SIZE | Cache size in bytes | 32768, 65536, 131072, 262144, 524288, 1048576, 2097152, 4194304 | 32768 | natural |
| C_CACHE_TAG_MEMORY_TYPE | Cache tag memory type | 0, 1, 2, 3 | 0 | natural |
| C_CACHE_DATA_MEMORY_TYPE | Cache data memory type | 0, 2, 3 | 0 | natural |
| C_CACHE_LRU_MEMORY_TYPE | Cache Least Recently Used (LRU) memory type | 0, 1, 2, 3 | 0 | natural |
| C_Lx_CACHE_LINE_LENGTH 1 |
Cache line length on masters connected to optimized ports. Automatically assigned with manual override |
4, 8, 16 | 4 | natural |
| C_Lx_CACHE_SIZE 1 |
Cache size on masters connected to optimized ports. Automatically assigned with manual override |
64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 | 1024 | natural |
| C_SUPPORT_SNOOP_FILTER | Support downstream snoop filter | 0, 1 | 0 | natural |
| C_SNOOP_KEEP_READ_ONCE | Keep allocation in cache after snoop of type ReadOnce (ACE) or SnpToAny (CCIX, CHI) | 0, 1 | 0 | natural |
| C_SNOOP_KEEP_READ_SHARED | Keep allocation in cache after snoop of type ReadShared (ACE) or SnpToS (CCIX, CHI) | 0, 1 | 0 | natural |
| C_SNOOP_KEEP_READ_CLEAN | Keep allocation in cache after snoop of type ReadClean (ACE) | 0, 1 | 0 | natural |
| C_SNOOP_KEEP_READ_NSD | Keep allocation in cache after ReadNotSharedDirty (ACE) | 0, 1 | 0 | natural |
| C_SNOOP_KEEP_CLEAN_SHARED | Keep allocation in cache after CleanShared (ACE) or SnpToC (CCIX, CHI) | 0, 1 | 0 | natural |
| C_SNOOP_KEEP_SNPTOSC | Keep allocation in cache after SnpToSC (CCIX) | 0, 1 | 0 | natural |
| C_SNOOP_PASS_READ_ONCE | Always pass write responsibility for snoop of type ReadOnce (ACE) or SnpToAny (CCIX, CHI) | 0, 1 | 0 | natural |
| C_SNOOP_PASS_READ_SHARED | Always pass write responsibility for snoop of type ReadShared (ACE) or SnpToS (CCIX, CHI) | 0, 1 | 0 | natural |
| C_SNOOP_PASS_READ_CLEAN | Always pass write responsibility for snoop of type ReadClean (ACE) | 0, 1 | 0 | natural |
| C_SNOOP_PASS_READ_NSD | Always pass write responsibility for snoop of type ReadNotSharedDirty (ACE) | 0, 1 | 0 | natural |
| C_DEFAULT_DOMAIN | Set default sharability domain for ACE Master
Coherency: 0 - Inner 1 - Outer |
0, 1 | 0 | natural |
|
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