Port Descriptions - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)
Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

CCIX Port Descriptions

The block diagram of the System Cache core configured for CCIX is shown in the following figure. All interfaces are compliant to AXI4, AXI4-Stream or CXS where applicable. The input signals ACLK and ARESETN implement clock and reset for the entire System Cache core.

Figure 1. CCIX Block Diagram System Cache Page-1 Process.492 System Cache System Cache Sheet.3 Arbiter Arbiter Process.4 Statistics + Control Statistics+Control Process.5 CCIX Coherency CCIX Coherency Sheet.17 8pt. Arial Text.491 AXI4 Slave Ports AXI4 SlavePorts Process.23 ATC ATC Process.24 ATC ATC Sheet.25 Sheet.26 Sheet.27 Sheet.28 Process.29 ATS ATS Sheet.30 Sheet.31 Sheet.33 Sheet.34 Sheet.35 Sheet.36 8pt. Arial Text.37 CQ_AXIS CQ_AXIS Sheet.38 8pt. Arial Text.39 CC_AXIS CC_AXIS Sheet.40 8pt. Arial Text.41 RC_AXIS RC_AXIS Sheet.42 8pt. Arial Text.43 RQ_AXIS RQ_AXIS Process.44 Cache + Coherency Hazard Handling Cache+CoherencyHazardHandling Sheet.45 Sheet.46 Sheet.48 8pt. Arial Text.49 CXS0_RX CXS0_RX 8pt. Arial Text.50 CXS0_TX CXS0_TX Sheet.51 8pt. Arial Text.52 S_AXI_CTRL S_AXI_CTRL Sheet.53 8pt. Arial Text.54 ARESETN ARESETN Sheet.55 8pt. Arial Text.56 ACLK ACLK Sheet.57 8pt. Arial Text.58 S3_AXI_GEN S3_AXI_GEN Sheet.59 8pt. Arial Text.60 S0_AXI_GEN S0_AXI_GEN 8pt. Arial Text.61 ATS AXI4-Stream Ports ATS AXI4-Stream Ports 8pt. Arial Text.62 CCIX CXS Ports CCIXCXSPorts Sheet.64 Sheet.65 8pt. Arial Text.66 Initializing Initializing 8pt. Arial Text.67 Interrupt Interrupt Sheet.1 X23134-063020 X23134-063020
Table 1. CCIX Interfaces
Name Type Description
ACLK Input Core clock
ARESETN Input Synchronous reset of core
Initializing Output Core is initializing after reset
Sx_AXI_GEN 1 AXI4 Slave Generic cache port
S_AXI_CTRL AXI4-Lite Slave Control port
CXS0_RX CXS Receive CXS interface
CXS0_TX CXS Transmit CXS Interface
CQ_AXIS AXI4-Stream Slave ATS CQ Interface
CC_AXIS AXI4-Stream Master ATS CC Interface
RC_AXIS AXI4-Stream Slave ATS RC Interface
RQ_AXIS AXI4-Stream Master ATS RQ Interface
Interrupt Output Control interrupt output
  1. x = 0 to 3

CHI Port Descriptions

The block diagram of the System Cache core configured for CHI is shown in the following figure. All interfaces are compliant to AXI4, AXI4-Stream or CHI where applicable. The input signals ACLK and ARESETN implement clock and reset for the entire System Cache core. The M0_CHI interface contains all 6 channels and the separate signals to handle link and system coherency handshake.

Figure 2. CHI Block Diagram
Table 2. CHI Interfaces
Name Type Description
ACLK Input Core clock
ARESETN Input Synchronous reset of core
Initializing Output Core is initializing after reset
Sx_AXI_GEN 1 AXI4 Slave Generic cache port
S_AXI_CTRL AXI4-Lite Slave Control port
M0_CHI CHI CHI Interface containing all 6 channels and extra signals
CQ_AXIS AXI4-Stream Slave ATS CQ Interface
CC_AXIS AXI4-Stream Master ATS CC Interface
RC_AXIS AXI4-Stream Slave ATS RC Interface
RQ_AXIS AXI4-Stream Master ATS RQ Interface
Interrupt Output Control interrupt output
  1. x = 0 to 3

AXI4/ACE Port Descriptions

The block diagram for the System Cache core is shown in the following figure. All System Cache core interfaces are compliant with AXI4. The input signals ACLK and ARESETN implement clock and reset for the entire System Cache core.
Figure 3. AXI/ACE Block Diagram System Cache Page-1 Process.492 System Cache System Cache Sheet.2 Arbiter + Optional Coherency Arbiter+OptionalCoherency Process.4 Statistics + Control Statistics+Control Process.5 Memory Controller Interface + Optional Coherency MemoryControllerInterface+ Optional Coherency Process.6 Cache + Optional Coherency Hazard Handling Cache+OptionalCoherencyHazardHandling Sheet.17 Sheet.18 Sheet.19 Sheet.20 8pt. Arial Text.115 S_AXI_CTRL S_AXI_CTRL Sheet.116 Sheet.117 8pt. Arial Text.118 ARESETN ARESETN Sheet.119 8pt. Arial Text.120 ACLK ACLK Sheet.121 8pt. Arial Text.122 AXI4/ACE Master Port AXI4/ACEMasterPort 8pt. Arial Text.123 M0_AXI/M0_ACE M0_AXI/M0_ACE 8pt. Arial Text.132 MicroBlaze Optimized AXI4/ACE Slave Ports MicroBlaze OptimizedAXI4/ACE Slave Ports Sheet.133 8pt. Arial Text.138 S15_AXI_GEN S15_AXI_GEN 8pt. Arial Text.140 S0_AXI_GEN S0_AXI_GEN 8pt. Arial Text.141 Generic AXI4 Slave Ports Generic AXI4 Slave Ports Sheet.142 Sheet.143 Sheet.144 Sheet.145 Sheet.146 8pt. Arial Text.148 S0_AXI/S0_ACE S0_AXI/S0_ACE 8pt. Arial Text.149 S15_AXI/S15_ACE S15_AXI/S15_ACE 8pt. Arial Text.151 Initializing Initializing Sheet.152 Sheet.23 X17763-062620 X17763-062620
Table 3. I/O Interfaces
Name Type Description
ACLK Input Core clock
ARESETN Input Synchronous reset of core
Initializing Output Core is initializing after reset
Sx_AXI 1 , 2 AXI4 Slave MicroBlaze optimized cache port
Sx_ACE 1 , 2 ACE Slave MicroBlaze optimized cache coherent port
Sx_AXI_GEN 1 AXI4 Slave Generic cache port
M0_AXI 3 AXI4 Master Memory controller master port
M0_ACE 3 ACE Master Master interface to ACE port on PS
S_AXI_CTRL AXI4-Lite Slave Control port
  1. x = 0–15
  2. Sx_AXI and Sx_ACE are mutually exclusive.
  3. M0_AXI and M0_ACE are mutually exclusive.