The Versal adaptive SoC programmable network on chip (NoC) is an AXI-interconnecting network used for sharing data between IP endpoints in the programmable logic (PL), the processing system (PS), and other integrated blocks. This device-wide infrastructure is a high-speed, integrated data path with dedicated switching. The NoC can be logically configured to represent complex topologies using a series of horizontal and vertical paths and a set of customizable architectural components.
The NoC was designed for scalability. It is composed of a series of interconnected horizontal (HNoC) and vertical (VNoC) paths, supported by a set of customizable, hardware implemented components that can be configured in different ways to meet design timing, speed and logic utilization requirements.
The HNoC and VNoC are dedicated, high-bandwidth paths connecting integrated blocks between the processor system and the PL without consuming large amounts of PL.
The NoC supports end-to-end quality of service (QoS) to effectively manage transactions and balance competing latency and bandwidth requirements of each traffic stream.
The NoC components comprise NoC master units (NMU), NoC slave units (NSU), NoC packet switches (NPS), and NoC Inter-Die-Bridge (NIDB). The NMU is the traffic ingress point; the NSU is the traffic egress point. All IPs have some number of these master and slave connections. The NIDB connects two super logic regions (SLRs) together, providing high bandwidth between dies. The NPS is the crossbar switch, used to fully form the network.
Horizontal Versus Vertical NoC
As shown in the following figure, NoC paths partition into HNoCs and VNoCs. The HNoCs are placed on both the bottom and top of the die. There are four bi-directional physical NoC channels in HNoC. While the bottom HNoC has four bi-directional physical channels in all devices, in the Prime and AI series devices the top HNoC has only two bidirectional physical channels. The bottom HNoC typically connects to a selection of blocks such as PS, Platform Management Controller (PMC), Integrated block for PCIe® with direct memory access (DMA) and cache coherent interconnect (CPM), and DDRMC (Integrated DDR Memory Controller) to list a few. The PS, PMC, and CPM are collectively referred to as Control, Interfaces and Processing System (CIPS). The HNoC consists of NoC components (NMU, NSU, NPS, and more). Similarly, the top HNoC typically connects to a selection of blocks such as DDRMC. For SSI technology devices, the top HNoC connects to NoC Inter-Die Bridge (NIDB) providing high bandwidth between two die.
The VNoC refers to the vertical NoC column. There are two bidirectional physical NoC channels in the VNoC. Each Versal device could have more than one VNoC. The VNoC connects to the PL. HNoC and VNoC are connected to provide a full NoC.
Design capture is achieved using the AMD Vivado™ IP integrator, from where you can specify the interconnectivity of all of the endpoints. Virtual Channels (VCs) (not shown) can be used to provide differential quality of service (QoS).